TestBencher Pro

1
TestBencher Pro

• Graphical Test Bench Generation for VHDL,
  Verilog, OpenVera, e, and C!

2
1.0 TestBencher Pro Overview

• Provides specification based verification
• Generates VHDL, Verilog, OpenVera, e, and C
  test benches from graphical timing diagrams
• Resulting code is modular, easy to debug, and
  compatible with all major VHDL and Verilog
  simulators
• Language independent timing diagrams enhance the
  ability of engineers to share data across
  projects
• The graphical interface speeds development for
  both expert and novice users, dramatically
  reducing the time necessary to create and
  maintain test benches

3
Specification Based Verification

• Problem Verify an SOC Model that interacts with
  different protocols

Solution Use TestBencher to define the
protocols, and then automatically generate the
transactors, transaction data, and logic to
verify the results.
1.1 Overview
4
Code Generation Process

• Create bus-functional models using
• Timing Diagrams to define reusable timing
  transactions
• Top-level template defines transaction sequence
  and monitors MUT status

1.2 Overview
5
Transaction Level Modeling

• TestBencher creates bus-functional models from a
  set of user created transactions.
• Examples of transactions are PCI bus cycles or
  microprocessor read and write cycles.
• Define each transaction with a timing diagram
• Define sequence of transaction calls
• tb_write.Execute_once('h20, 'hEE, 10)
• tb_read.Execute_once('h20, 'hEE, 10)
• User writes code at the transactional level

1.3 Overview
6
Timing Diagrams Communicate Transaction Behavior

• HDL Code
• Simplest signal behavior difficult to communicate
• Code complexity greatly increases for
• response checking code
• parallel execution blocks

• module testbench
• ...
• task write(addr,data,csb2dbus)
• input 70 addr
• input 150 data
• input 10 csb2dbus
• begin
• ABUS addr
• _at_(posedge CLK0) //required abus2csb setup
• CSB 1'b0
• repeat (csb2dbus) _at_CLK0
• DBUS data
• _at_(posedge CLK0)
• CSB 1'b1
• DBUS 'hz
• ABUS 'hz
• end
• endtask
• ...

• Graphical Representation
• Concisely communicates transaction behavior

1.4 Overview
7
Transactions are Reusable

• Supports State and Timing parameter variables
• Set parameters at runtime with function calls
• Set parameters from data files for regression
  testing
• Express runtime-computable timing relationships
  between signal transitions

State Parameters Apply_tbread('h20, 'hEE,
10.5) Timing Parameter
1.5 Overview
8
Transaction Manager

• Transaction Manager maintains a queue of
  transactions to be executed. Accepts transactions
  from many sources

• Transactions read from a file
• Other BFM models in the verification hierarchy
• Transaction Apply calls made by the user in the
  template file
• Randomly generated transactions produced by the
  Transaction Generator
• Transactions spawned by other transactions

1.6 Overview
9
Transaction Monitor Generator

• Transaction Monitor and Generator work together
  to accumulate statistics on what transactions
  occur, and then dynamically adjust the
  randomization constraints to ensure important
  test cases are covered.

1.7 Overview
10
2.0 Advanced Features

• Hierarchical BFM Components
• Golden Reference Model
• Automatic generation of file I/O code
• Fast conversion from time- to cycle-based test
  benches
• External Simulation and Compiler Control

11
Hierarchical BFM Architecture

• TestBencher Pro uses a project file to control
  the generation of a bus-functional model
• Projects can be included hierarchically in other
  projects
• Multiple Instantiation of test bench components
• Multiple Port Testing supported
• Reuse test bench models as sub-components to
  another test bench model

2.1 Advanced Features
12
Golden Reference Model

• Golden Reference Models are high-level
  descriptions of a system that are used to
  automate the verification of system output
• Generates all of the stub functions for golden
  model
• User writes behavioral code inside stub functions
• Automatically compares MUT output against golden
  reference model during simulation and reports
  errors

2.2 Advanced Features
13
Automatic Generation of File I/O Code

• Test-vector spreadsheet format used for file I/O
• Read from or Write to a record structure
• Import state and timing information
• Export data collected by samples
• Quickly generate tedious file I/O code using file
  associations
• Easily swap between using a test-vector file or
  function calls to control transaction state and
  timing parameters

2.3 Advanced Features
14
Switching between Time-based and Cycle-based test
benches

• Supports time and cycle-based test benches
• Specify a clock signal to switch to cycle based
• All signals, delays, samples, and markers have
  the clocking feature
• Supports sensitivity to multiple clock edges
• positive, negative, or both clock edges
• Supports multiple clocks

2.4 Advanced Features
15
External Simulator Control

• TestBencher Pro controls compilation and
  simulation
• One environment for test development and design
  debug
• Handles simulators and compilers running on
  different operating systems and remote machines
• Graphically display simulation results and log
  files

2.5 Advanced Features
16
VHDL, Verilog, C

• C Library Support using TestBuilder
• Constrained Random Data Structure Generation
• External control of simulator and compiler

2.6a Advanced Features
17
VERA and OpenVera Support

• Graphical environment for generating OpenVera
  test benches
• Data structure code generation for classes,
  arrays, associative arrays, and queues.
• Samples generate OpenVera expects.
• Constrained Random Data support through a
  graphical interface in the data structures
  dialog.
• Remote execution of VERA and HDL simulator for
  seamless development and debug

2.6b Advanced Features
18
Specman Elite and e Support

• Graphical environment for generating e test
  benches
• Data structure code generation for structs,
  arrays, associative arrays, and queues.
• Samples generate e Temporal Expressions
• Constrained Random Data support through a
  graphical interface in the data structures
  dialog.
• Remote execution of Specman Elite and HDL
  simulator for seamless development and debug

2.6c Advanced Features
19
3.0 Transaction Examples

• TestBenchers Transactions can express complex
  protocol behavior
• Sequence Recognition with Graphical Samples
• Trigger Delayed Events and Conditionally Sample
• Constrained Random Data Structures
• Concurrent Timing Transactions
• TestBencher has been used to generate bus
  functional models for some of the most advanced
  systems
• PCI Burst Mode
• ATM File Output
• ARM Pipelining Transactions

20
Trigger Delayed Events and Conditionally Sample
Values

• Graphical Samples can be used to
• Trigger Delays and other Samples to set up a
  logical path of diagram execution and error
  checking.
• Write sampled data to memory which can be used to
  drive states or used to compare against other
  states later in the same simulation or in another
  simulation run.
• These triggered events can be chained

3.1 Transaction Examples
21
Sequence Recognition

• Use graphical Samples to monitor MUT during
  simulation
• Verify Sequence of Events before allowing
  transaction to proceed.
• Verify a Particular Cycle before responding

3.2 Transaction Examples
22
Constrained Random Data Structures

• Create Data Structure once and use it anywhere in
  the test bench project or save it in a reusable
  library
• Control Random Data generation for each field
• Create Memories, FIFOs, and Stacks for driving
  Tests

3.3 Transaction Examples
23
Concurrent Timing Transactions

• Sequencer Process controls order in which
  transactions are applied to the MUT.
• Transactions can run sequentially in a blocking
  mode or concurrently.
• Transactions can be set to run once or run in a
  continuously looping mode
• Transaction calls are automatically generated
  using a dialog interface

3.5 Transaction Examples
24
PCI Burst Mode

• This diagram models a PCI master device.
• A loop is used to parameterize the number of data
  cycles to perform.

3.6 Test Bench Examples
25
ATM File Output

• This slave transaction receives data cells from
  an ATM switch.
• Samples are used to output the ATM cells to a
  spreadsheet formatted file.

3.7 Transaction Examples
26
ARM Pipelining Transactions

• This diagram models an ARM master device.
• The pipeline nature of the bus is simulated using
  a set of queues and cycle loops. The value of the
  data bus is read by samples and then stored in a
  queue. The data bus value is then read from the
  queue for write cycles.

3.8 Transaction Examples
27
4.0 Basic Design Flow

• Four-step process to create test benches
• 1) Add model under test and extract port
  information
• 2) Create re-usable transactions from timing
  diagrams
• 3) Sequence transactions in top-level module
• 4) Generate test bench

28
Step 1 Add Model Under Test and Extract Port
Information

• Add Model Under Test (MUT) to project
• Verilog and VHDL parsers
• automatically extract port information
• automatically extract signal properties
• Data extracted at any level of the MUT

4.1 Basic Design Flow
29
Step 2 Create Reusable Timing Transactions

• Use built-in timing diagram editor to create
  reusable timing transactions
• Parameterize state and timing values using
  variables
• Color indicates driven/expected states in
  waveform
• Samples verify and react to response of model
  under test

4.2 Basic Design Flow
30
Step 3 Sequence Transactions in Top Level Module

• Top-Level code generated from template files
• Instantiate the model under test
• Add transaction calls. For example,
• Apply_tbread()
• (Optional) Add any other top-level processing
  code. For example,
• for or while loops
• function calls

-- Sequencer Process process variable delay0
real begin tb_initialize_SweepTest(SweepTest)
Apply_gClock_looping_nowait(SweepTest,
100.0) for i in 0 to 5
loop delay0 real (32 - (i 5))
Apply_tbwrite(SweepTest, xF0,
xAE, delay0) Apply_tbread(SweepTest,
xF0, xAE, delay0) end
loop wait Abort_gClock(SweepTest) end
process
4.3 Basic Design Flow
31
Step 4 Generate Test Bench and Simulate

• Automatically generate test bench
• Template macros are expanded
• User written code remains
• Test Bench files needed for Simulation
• One file for top-level test bench
• One file for each timing diagram (transaction)

4.4 Basic Design Flow
32
5.0 Graphical Constructs

• Simple set of graphical constructs naturally
  express timing and bus protocols
• Waveforms - stimulus and expected response
• Variables - parameterize state and timing values
• Delays - parameterize time delays
• Samples - verify and react to output from MUT
• Markers - model looping constructs, insert native
  HDL subroutine calls, or end transaction

33
Waveforms Provide Stimulus and Expected Response
Information

• Several methods available for waveform entry
• Graphically draw stimulus/response waveforms
• Generate waveforms using RTL-level equations
• Import from simulators VHDL, Verilog, SPICE
• Import from logic analyzers Agilent, Tektronix
• Import state information from spreadsheets

5.1 Graphical Constructs
34
Variables Parameterize State Values

• State Variables control bus states during
  simulation
• Variables can be read from a file like
  _at_readData.dbus70 passed into the transaction
  as a function parameter like addr
• Variables can be specified as conditional
  expressions including Boolean equations that
  reference state variables and user-defined data
  structures.

5.2 Graphical Constructs
35
Delays Parameterize Time Values

• Delays can conditionally control when edges occur
• Delay values can be time or cycle-based
• Delay values can be passed in from a function
  call or read in from a file

5.3 Graphical Constructs
36
Samples Verify MUT Output

• Sample constructs can monitor and perform actions
  based on the data sampled
• Sample can work at a single point or over a
  windowed area
• They can perform relative to the beginning of the
  transaction or relative to another event in the
  diagram.

5.4 Graphical Constructs
37
Markers used for Control Looping Sections of
Transactions

• Specify the End of Transaction
• Create loops
• Insert HDL code
• Useful for generating conditional burst type
  transactions

5.5 Graphical Constructs
38
Summary

• TestBencher Pro reduces the time required to
  create and maintain test benches in VHDL,
  Verilog, OpenVera, e, and SystemC.
• Features include external simulator control,
  sequence recognition, conditional execution,
  hierarchical, and multiple instantiation of test
  bench projects
• TestBencher can model the most advanced
  verification problems PCI, ARM, and ATM
• Easy four-step process to create a test bench
• Timing Diagrams are a natural way to express
  timing protocols.

39
Contacts

• Visit our Web site at www.syncad.com
• Call us at 1-540-953-3390
• Download and install, then request a free 30-day
  license