ECE6130: Computer Architecture: Instruction Set Architecture

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ECE6130 Computer ArchitectureInstruction Set
Architecture

• Dr. Xubin He
• http//iweb.tntech.edu/hexb
• Email hexb_at_tntech.edu
• Tel [phone], Brown Hall 319

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• Previous Class
• Memory addressing
• Today
• Operands and operations

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Type and Size of Operands

• Encoding in opcode designates the type of operand
• Data can be annotated with tags interpreted by
  hardware (in museums)
• Desktop and Server architectures
• Character (8 bits), half word (16 bits), word (32
  bits), single-precision FP (also 1 word), and
  double-precision FP (2 words)
• Some business apps have decimal format called
  packed decimal 4 bits are used to encode values
  0-9, and 2 decimal digits are packed into each
  byte
• Accurately match decimal numbers
• See figure 2.12
• Frequency of access to different data types
  decide what type are most important to support
  efficiently
• A 64-bit access path, or taking 2 cycles to
  access a double word

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Figure 2.12 Distribution of data accesses by size
for benchmark programs
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Operations in ISA

• Operator Types
• Simple operation instructions dominate most
  instruction executed
• Arithmetic and logical , -, and, or
• Data transfer load-stores (move inst)
• Control branch, jump, procedure call and
  return
• System OS call, VM management inst
• Floating point add, multiply
• Decimal decimal add, decimal multiply
• String string move, compare
• Graphics pixel and vertex Ops, compression/de
  Ops
• 80x86 as an example, see figure 2.16

Basic System functions
various
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Figure 2.16
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About Registers

• A register is an array of flip-flops with special
  properties
• Registers are the fastest kind of addressable
  memory
• Registers are located on the same die as the
  processor
• Registers are NOT located in main memory, L0
  cache!
• The set of registers in a processor is called the
  register file
• Registers are addressed separately differently
  from main memory
• MIPS R2000 architecture
• Main memory addresses are 32 bits
• 4,294,967,296 addressable 8-bit bytes
• Register addresses are 5 bits
• 32 addressable 32-bit general-purpose registers
• Register addresses run from 000002 010 to
  111112 3110
• MIPS assembler Register addresses are written
  0, , 31

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About Registers
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More about ISA

• Why register architectures are dominant?
• Since 1980, logic circuits have become much
  faster than dynamic RAM
• Registers are faster than main memory
• Registers are faster than stack
• A stack is built in main memory
• Operands that are in registers can be used in any
  order
• Registers can hold variables as they are updated
  in a multi-step computation
• Reduction of main memory traffic makes
  computations faster
• Register addresses (typically 5 bits) are shorter
  than main memory addresses (typically 32 to 64
  bits)
• Code density (information per bit in an
  instruction) is higher than in Load-Store archs
  than in archs allow memory-resident operands
• Short, fixed addressing ? fixed length
  instructions
• For a register machine, one can optimize the most
  frequently used instructions (which are very
  simple, by experiments)

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More on addressing modes
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Addressing Modes for Control Flow Instructions

• Must specify the destination address of a control
  flow instruction
• Mostly be specified explicitly in the instruction
• Procedure call is exception
• PC-relative addressing
• Problem Procedure return the target is unknown
  at compile time
• Solution supply a displacement added to program
  counter (PC)
• Pros
• target near current instruction
• specifying the position relative (delta) to PC
  requires fewer bits
• Permits the code to run independently of where it
  is loaded
• Position independence, eliminate some work when
  the program is linked and is also useful in
  programs linked dynamically during execution

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Assume MyProgram is the main executable program,
Strcmp() is a call procedure and statically
linked with MyProgram.
1000
MyProgram needs to call strcmp()
Loadrel 100PC
Offset 100
100
1100
Strcmp().
1000
Main Memory
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Register indirect jump

• Register indirect jumps
• Problem Target unknown at compile time
• Solution naming a reg that contains the target
  adr
• Register indirect jumps support following
  features in programming languages
• Case or switch statements
• Virtual functions or methods in OOP programming
• High-order functions or function pointer like C
  or C
• Dynamically shared libraries

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Assume MyProgram is the main executable program,
Strcmp() is a call procedure and dynamically
linked with MyProgram.
1000
MyProgram needs to call strcmp()
Load R31
R31
1100
1100
strcmp().
Main Memory
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Instruction for Control Flow

• Types of Control Flow Instruction
• Jump unconditional control transfers
• Branch conditional
• Procedure calls
• Procedure returns
• See figure 2.19
• See figure 2.30 for typical control flow
  instructions in MIPS
• All control instructions, except jumps to an
  address in a register, are PC-relative

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Figure 2.19 breakdown of control flow instructions
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How to specify branch conditions

• Most changes in control flow are branches ? how
  to specify the branch conditions
• Three primary techniques
• Condition code (CC) 80x86, PowerPC, SPARC
• Condition register Alpha, MIPS
• Compare and branch VAX, PA-RISC
• Compare and Branch
• Many branches are simple equality or inequality
  tests
• Large fraction are comparisons with zero
• Frequency of different comparisons used for
  conditional branching, see figure 2.22

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Figure 2.22 frequency of different types of
compares in conditional branches
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Procedure Calls/Returns

• Procedure calls/returns include some state saving
• For sure, the return address in a procedure call
• Sometimes, a GPR
• Sometimes the whole reg set in a procedure call
• If compiler has to save regs, 2 conventions are
  possible
• Caller saving calling procedure has to save the
  regs it wants preserved for access after the call
• Callee saving called procedure must save the
  regs it wants to use
• Compiler prefers caller saving to avoid
  complications from global variable allocations
• P1 calls P2 and both have a global variable x,
  save to a Reg, and must save x to a place P2
  knows before call P2.
• Why?

Because even P2 does not touch x, its
sub-procedure P3 may still access x!
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Destination of Branches

• Most branches are forward (75)
• Most branches branch to nearby locations
• See figure 2.20
• The most frequent branches in the integer
  programs are to targets that can be encoded in
  4-8 bits
• Short displacement fields suffice for branches ?
  Gain encoding density by having a shorter
  instruction with a smaller branch displacement

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Figure 2.20 branches distances tested on L/S Alpha
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Encoding an Instruction Set

• Operation is encoded in a field Opcode
• How to encode the addressing modes with
  operations?
• Depends on the range of addressing modes and the
  degree of independence between opcodes and modes
• If many addr modes/operands gt use a separate
  address specifier for each operand
• Ex., 1-5 operands with 10 adr modes for each
  operand (Fig. 2.6)
• Address specifier tells what addressing mode is
  needed for each operand
• If (in a load-store machine) one mem operand and
  one/two addressing modes gt encode the addressing
  mode as part of opcode
• Need field(s) for encoding reg. And (maybe) addr
  mode, of regs and of addr modes ? instruction
  size

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Encoding an Instruction Set

• Balance several competing forces
• Have as many regs and addr modes as possible
• Impact of the size of the reg and addr mode
  fields on avg inst size ? program size
• Desire to have inst encodes into lengths easy to
  handle in a pipelined implementation
• Many desktop and server architects have chosen to
  use a fixed-length inst to gain implementation
  benefits while sacrificing avg code size

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Figure 2.23
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• E.g., Intel 80x86 instruction (variable encoding)
• add EAX, 1000(EBX) 6 bytes

1000 gt 28, need 4 bytes
32 bit integer add with 2 operands This opcode
is 1 byte
Addr specifier is 1 or 2 bytes Specifying
src/des reg(EAX), AM, and base reg(EBX)?1 byte
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Reduced code size in RISC

• Hybrid version of RISC
• Both 16-bit and 32-bit inst
• Fewer ops, smaller addr and immediate fields,
  fewer regs, two addr format than classic three
  addr
• ARM Thumb and MIPS 16
• Inst cache is 25 bigger
• IBM CodePack
• Compress standard Inst set, add HW to decompress
  inst as fetched from mem on an inst cache miss
• Compressed code kept in mem
• 10 overall performance loss but 35-40 code
  size reduction gain

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Next

• Role of compiler