PSPICE?????

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PSPICE?????

• Simulation Program with Integrated Circuit
  Emphasis

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CH7

• THE STEP RESPONSE AND SWITCHES
• ????

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7.1 Simple step response
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Fig. 69
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Example 11

• a) The switch in the circuit shown in Fig. 69 is
  closed at t0. At the instant the switch is
  closed, the initial current in the 10 mH inductor
  is 90 mA, and the voltage across the capacitor is
  10 V.

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• Fig. 69 also shows the references for these
  initial conditions. Make a preliminary analysis
  of the step response, and calculate the maximum
  value of Vc and the time at which it occurs.

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• b) Create a PSpice schematic, perform transient
  analysis, and plot Vc versus t from 0 to 3000 µs.
• c) Compare the PSpice solution with the
  preliminary analysis.

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Solution a)

• From the solution of Example 10, we already know
  that the response is underdamped.
• Furthermore, we know that the damped period is
  897.60 µs, and that

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• The step-response solution for Vc takes the form

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• The initial values of Vc and dVc/dt are the same
  as in Example 10, and the final value is 21 V.
  Hence B1-31 V and B22 V, so

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• The maximum value of Vc is 41.22 V at 419.32 µs.

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Solution b)

• In Fig. 71, we used two cursors this time, and
  moved the second cursor by holding down the Shift
  key while using the left and right arrow keys.
  The cursors allow you to read the values of Vc
  (max) and Td directly from the Probe plot.

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Fig. 70 schematics
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Fig. 71 probe
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Solution c)

• The output of the PSpice analysis yields

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7.2 Piecewise Linear Sources (??????)

• Example 12 illustrates the use of the piecewise
  linear source for modeling the switching that
  takes place in a transient analysis problem.

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Example 12

• The circuit shown in Fig. 72 has been in
  operation for a long time. At t0, the 80 V
  source drops instantaneously to 20 V. Construct a
  PSpice schematic, using a PWL source, to model
  this circuit. The results of the analysis should
  be a plot of Vo (t) versus t.

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Solution
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Fig. 73 Ex12_ddb
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Fig. 74 Schematic
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• ??V2 ???
• V2?? (Fig. 75)

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Fig. 75 PWL Property Editor
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Fig. 75a Simulation Profile
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Fig. 76 Probe
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Results

• The Probe plot in Fig. 76, which uses the cursors
  to determine the output voltage at t40 ms and
  t80 ms, yields the following results
• t Vo(t)
• 0 64
• 40 33.698 (??33.654)
• 80 22.489 (??22.498)

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• Furthermore, you can see from the Probe plot that
  Vo(t) approaches 16 V as t approaches 8.

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7.3 Realistic Switches (????)

• We illustrate the use of the normally-opened
  switch in Example 13 to examine the effect of
  nonzero switch resistance on the step response of
  the RLC circuit.

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Fig. 69
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Example 13

• Use PSpice to model the circuit shown in Fig. 69,
  with some modifications.
• Assume that the voltage source is the same as
  that used in Example 10, and use the same values
  in specifying transients analysis.
• But assume that the resistance of the switch in
  the ON position is 10 ?.

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• Then generate a plot of Vc versus t. Compare the
  results here with those in Example 10.

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Fig. 77 Schematic
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Components

• EVAL/Sw_tClose

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Fig. 78 Property
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Fig. 79 Probe