VerilogA Validation Suite Proposals

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Verilog-A Validation Suite Proposals

• Geoffrey Coram

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Verilog-A Validation Suite

• CMC officers proposed using budget surplus for
  Verilog-A validation suite
• Contacted various experts
• Proposals received
• Prof. Richard Shi, U. Washington MCAST compiler
  (VHDL-AMS) beats hand-coded C
• Prof. Al Davis, Kettering U. active member of
  Verilog-AMS compact modeling subcommittee, author
  of GNUCAP
• Tiburon Design Automation proposal missed
  deadline

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Richard Shi

• Budget 50k
• Two graduate students for half a year travel
• Objectives
• (1) Develop a set of canonical Verilog-A
  compact model examples to cover all the needed
  features (completeness), based on industry
  standard MOS and bipolar models (BSIM, EKV, PSP,
  HICUM, etc.) and test these examples on
  participating Verilog-A compilers (commerical and
  public domain).
• (2) To assist the implementation of emerging
  MOSFET, bipolar, and resistor models using
  Verilog-A and model compilers.
• Goals
• Phase I -- feature completeness
• Phase II -- efficiency testing
• Deliverables
• (a) A set of examples
• (b) Script (a tool) to automate the validation
  process.
• (c) A Validation report.

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Al Davis

• Budget 10k
• One graduate student for one quarter, plus
  overhead
• Framework
• Test files for Verilog-A (analog subset of AMS)
  version 2.2 and 1.0
• Also include bad files to test error reporting
• Expect more than 1000 files
• Wrapper scripts to invoke simulators in batch
  mode
• Test files
• 1. Basic test files for basic framework of the
  language.
• 2. Detail test files section by section testing
  of the LRM with simple tests of specific details.
• 3. Composite test files to test groups of
  features working together.

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Verilog-A Validation Suite

• For the CMC to decide
• Scope of project
• 10k or 50k?
• When are results needed?
• One-time suite creation, or continuing
  development?
• University team versus commercial
• Industrial knowledge and experience (or fox
  guarding henhouse?)
• Modeling expert versus compiler expert
• Modeling expert sure to test correlated noise,
  NQS
• Compiler expert may lead us more quickly to where
  Verilog-A compilers are as mature as C
  compilers