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3 The Digital Logic Level

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Clocked SR Latches. Prevent the latch from changing state except at certain specified times. Enable, or strobe: mean that the clock input is 1. Clocked D Latches ... – PowerPoint PPT presentation

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Title: 3 The Digital Logic Level


1
3 The Digital Logic Level
  • 3.1 Gates and Boolean algebra
  • 3.2 Basic digital logic circuits
  • 3.3 Memory
  • 3.4 CPU chips and buses
  • 3.5 Example CPU chips
  • 3.6 Example buses
  • 3.7 Interfacing
  • 3.8 Summary

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3.1 Gates and Boolean algebra3.1.1 Gates
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Major IC families
  • TTL-IC (Transistor-Transistor Logic IC)
  • runs on 5 volts.
  • workhorse of digital electronics.
  • MOS-IC (Metal Oxide Semiconductor IC)
  • varieties PMOS, NMOS, CMOS
  • CMOS runs on 3.0 9 volts
  • ECL-IC (Emitter-Coupled Logic IC)
  • used when high-speed operation is required,
    e,g, supercomputer.

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3.1.2 Boolean algebra
What is Boolean algebra (switching algebra)? It
is an algebra for the manipulation of objects
that can take on only two values, typically true
and false, although it can be any pair of values.
Boolean operators AND OR
NOT
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Boolean expression
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Boolean expression
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Boolean expression
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Boolean expression
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Boolean expression
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  • Generally, for n inputs, X1, X2, , Xn, there are
    2n possible combination of the values. The output
    Yf(X1, X2, , Xn) takes 0 or 1.

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3.1.3 Implementation of Boolean functions
  • How to implement a circuit for any Boolean
    function?
  • Write down the truth table for the function.
  • Provide inverters to generate the complement of
    each input.
  • Draw AND gate for each term with a 1 each result
    in each result column.
  • Write the AND gates to the appropriate inputs.
  • Feed the output of all the AND gates into an OR
    gate.

It is not the best answer!
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Example Implement the majority logic function
Mf(A,B,C). Here, majority logic function means
that M is 0 if a majority of its inputs are 0,
and 1 if a majority of its inputs are 1.
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3.1.4 Circuit equivalence
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Example Find the Boolean expression and truth
table for the following circuit.
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3.2 Basic digital logic circuit3.2.1
Integrated circuits
IC integrated circuits. SSI (Small Scale
Integrated) circuit 1 to 10 gates MSI (Medium
Scale Integrated) circuit 10 to 100 gates LSI
(Large Scale Integrated) circuit 100 to 100,000
gates VLSI (Very Large Scale) circuit gt 100,000
gates IC packages DIP Dual Inline Package QFP
Quad Flat Package PGA Pin Grid Array PPGA
Plastic PGA CPGA Ceramic PGA
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3.2.2 Combinational circuits
Combinational Circuits Circuits in which the
outputs are uniquely determined by the current
input.
X1
Combinational circuit
Y1
X2
Y2


Xn
Ym
Yjf(X1, X2, , Xn) (j1, 2, , m)
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Multiplexers 2n data inputs, n control inputs
output one of 2n data inputs
e.g. n3
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Decodersn inputs select one of 2n output line.
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Comparators
A(A3A2A1A0)2 B(B3B2B1B0)2
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Programmable logic arrays
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3.2.3 Arithmetic Circuits Shifters
C0, shift one-bit to the left ( times 2). C1,
shift one-bit to the right ( divided by 2).
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AddersHalf adder add two digits without
considering carry in.
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Full adder add two digits and carry in.
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Ripple carry adder (16-bit)
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Under normal condition ENA1 ENB1 INVA0
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3.2.4 Clocks
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3.3 Memory3.3.1 Latches
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Clocked SR Latches
  • Prevent the latch from changing state except at
    certain specified times.
  • Enable, or strobe mean that the clock input is 1

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Clocked D Latches
To solve the SR latchs ambiguity (caused when
SR1) is to prevent it from occurring.
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3.3.2 Flip-Flops
Flip-flop the state transition does not occur
when the clock is 1 but during the clock
transition from 0 to 1 (rising edge) or from 1 to
0 (falling edge).
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Difference between flip-flop and
latch Flip-flop edge trigged Latch level
triggered
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Latches
Flip-flops
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3.3.3 Registers
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  • Register Flip-flops are group together to store
    data.
  • 8-bit register

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3.3.4 Memory Organization
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3.3.5 Memory Chips
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3.3.6 RAMs and ROMs
SRAM Static Random Access Memory, DRAM Dynamic
RAM ROM Read-Only Memory, PROM Programmable
ROM EPROM Erasable PROM EEPROM Electric
Erasable PROM Flash memory block erasable and
rewritable
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