Lecture 9 Design

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Lecture 9Design Leakages of Low-Voltage CMOS
Devices

• Circuit design style
• Leakage current in deep submicron transistors
• Summary

• Michael L. Bushnell
• CAIP Center and WINLAB
• ECE Dept., Rutgers U., Piscataway, NJ

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Introduction

• Lower MOS supply voltages save energy
• Require low transistor threshold voltages
• Causes sub-threshold leakage currents to be
  significant
• Need to control leakage currents with device
  design
• Need to run slower parts of circuit at lower
  voltage
• Circuit design style (type of CMOS logic) is
  critical
• High leakages require modified IDDQ testing
• Modify to account for operating frequency

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Power Versus Supply and Vt
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Non-Clocked Logic

• Static CMOS
• nMOS
• Pseudo-nMOS
• Differential Cascode Voltage Switch (DCVS) Logic
• Pass Transistor Logic

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Static CMOS

• Easy to design
• Uses low power
• Low sensitivity to noise and process variations
• High noise margin
• Scalable
• Lower performance for large fanin gates,
  especially in pMOS tree
• Power due to short-circuit, switching, and
  glitching currents
• Standby mode power only due to leakages
  (neglect)

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nMOS Logic

• Ratioed logic R LOAD gt 4 X RPull-down

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Pseudo-nMOS Logic
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Pseudo-nMOS Logic

• Less complex than static CMOS, so lower CL,
  faster
• Unlike nMOS, load device unaffected by body
  effect
• Ratioed design style good for large fanin
  NAND/NOR
• Uses more power than static CMOS
• Power always flows when pull-down network on

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Differential Cascode Voltage Switched Logic (DCVS)
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DCVS Logic

• No static power dissipation
• Faster (than static CMOS) because of ratioed
  logic
• Two pull-down network functions are complementary
• Larger area and switched capacitance
• Inverters rarely needed
• Sometimes can share hardware between two
  pull-down networks

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Pass Transistor Logic

• Switches in series implement AND function
• Switches in parallel implement OR function
• Fast, but transmits logic 1 as VDD Vtn
• Needs logic level restorers

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Complementary Pass Transistor Logic (CPL)
AND/NAND
B
B
A
AB
B
A B
A
B
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Complementary Pass Transistor Logic (CPL)
XOR/XNOR

A B
A B

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Complementary Pass-Transistor Logic (CPL)

• Advantages
• Differential output signals
• Modular
• Reduced internal CL low power
• Can support reduced voltage swing
• 32-bit Adder CPL has 10 lower power-delay
  product than static CMOS

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Clocked Logic

• Domino Logic
• Differential Current Switch Logic (DCSL)
• Uses less power than Domino logic
• Higher performance at expense of higher power
  dissipation

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Domino Logic

• Keeper transistor very useful with leaky
  transistors

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Domino Logic

• Only implements non-inverting logic gates
• Very good for large fanin gates NAND/NOR
• Inputs connect only to 1 transistor reduced CL
• Increased signal activity extra loads for clock
  line
• High power usage compared with static CMOS
• Many glitches due to clock
• Spurious transitions not possible on output
• Not as scalable as static CMOS
• Lower noise immunity, so need higher Vt

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Differential Current Switch Logic (DCSL) Gate
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Differential Current Switch Logic

• DCVS logic gate modified to reduce internal node
  voltage swings
• T2, T3, T6, T7 cross-coupled inverter pair
• T1 T4 Precharge outputs high
• Note T12 sometimes needed to prevent internal
  node charge buildup
• Advantage Once evaluation completed, high output
  is disconnected from n-tree, so further input
  changes ignored
• No static paths from VCC to ground at end of
  evaluation
• Can get completion signal by NANDing two outputs
• Internal node swings for DCSL (DCSL2) are 1 V
  (0.3 V)

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DCSL Gate Operation

• When CLK low, Q and Q precharged high
• When CLK high, nMOS tree inputs must be stable
• T9, T10, T11 switched on by high CLK
• Precharged outputs switch on T5, T6, T7, T8
• Q and Q discharge asymmetrically towards ground
• One of the paths to ground is stronger (say Q)
• So, Q falls faster than Q
• Cross-coupled inverter functions as sense
  amplifier
• Boosts output voltage differential in the right
  direction, so Q swings high
• Logic limits charge-up of internal nodes of nMOS
  tree to voltages much smaller than VCC
  Vtn (limit for DCVS Logic)

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DCSL2 Gate (Precharged Low)

• CLK high is precharge, CLK low is evaluation
• Degraded gate propagation delay

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DCSL3 (Best Version)

• Removed T9 and T10, replaced with T9
• Precharge Q and Q to Vtn or lower
• Saves power, faster than DCSL2 (less O/P voltage
  swing)

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Energy Consumption
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CLK-to-Q Delay 90 / 10
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CLK-to-Q Delay 50
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Energy X Delay vs. n-Tree Height
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Leakage Current in Deep Submicron Devices

• Transistor off-state current when VGS 0
• Long-channel devices dominated by
• Drain-well leakage
• Well-substrate leakage
• Short-channel devices dominated by
• Vt
• Channel physical dimensions
• Channel/surface doping profile
• Drain/source junction depth
• Gate oxide thickness
• VDD, drain, and gate voltages

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Transistor Leakages
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Transistor Leakages

• I1 pn Reverse-Bias Current
• I2 Weak Inversion
• I3 Drain-Induced Barrier-Lowering (DIBL) Effect
• I4 Gate-Induced Drain Leakage (GIDL)
• I5 -- Punchthrough
• I6 Narrow-Width Effect
• I7 Gate Oxide Tunneling
• I8 Hot-Carrier Injection

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pn Reverse-Bias Current

• Minority-carrier drift near edge of depletion
  region
• Electron-hole pair generation in depletion region
  (reverse-biased junction)
• If heavily doped, Zener tunneling may also happen
• MOSFET added leakage
• Between drain and well junction (due to overlap
  of gate to drain to well pn junctions)
• Carrier generation in drain-to-well depletion
  regions
• pn reverse-bias leakage f (junction area,
  doping)

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Weak Inversion in 3.5 mm Technology Dominates
Leakage

• Happens in nFET when gate is below Vt
• Carriers diffuse through channel (no horizontal E)

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CMOS Technologies
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Subthreshold Swing (Slope) St

• Has not increased with new technologies because
  tox got smaller and substrate doping profiles
  improved
• Value of St 100 mV/decade is unacceptable

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Drain-Induced Barrier-Lowering

• Depletion region of drain interacts with source
  near channel surface
• Lowers source potential barrier
• Causes source to inject carriers into channel
  surface independently of gate voltage
• More DIBL at higher VD and shorter Leff
• Surface DIBL happens before deep bulk
  punchthrough
• Fix DIBL
• Higher surface channel doping
• Shallow source/drain junction depths

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DIBL Effects

• Moves curve up, to right as VD increases
• VD going from 0.1 to 2.7 V, ID changed 1.68
  decades
• DIBL 1.55 mV/decade change of ID

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Gate-Induced Drain Leakage

• Generates carriers into substrate and drain from
  surface traps or band-to-band tunneling
• Due to high electric field under gate/drain
  overlap region that causes deep depletion
• Happens at low VG and high VD bias
• Localized along channel width between gate and
  drain
• Appears as hook in last figure
• Increasing current for negative VG values
• Major problem in Ioff current
• Caused by thinner tox, higher VDD, and lightly
  doped drains

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Punchthrough

• Happens when drain and source depletion regions
  approach each other and touch
• Lets channel current exist deep in sub-gate
  region
• Gate loses control of sub-gate region
• Varies quadratically with VD and with St
• Viewed as subsurface version of DIBL

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Narrow-Width Effect

• Trench isolation
• Dig trench in substrate and fill with SiO2 to
  isolate n and p MOSFETs
• Non-trench isolated technologies
• Vt increases for gate widths of 0.5 mm
• Trench isolated technologies
• Vt decreases for effective channel widths W
  0.5 mm

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Gate Oxide Tunneling

• High Eox electric field across oxide layer
  causes
• Direct electron tunneling through gate
• Fowler-Nordheim (FN) tunneling through oxide
  bands (usually only at higher Eox than chips use)
• Currently a non-issue, expected to become
  dominant leakage condition as oxides get thinner

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Tunneling
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Hot-Carrier Injection

• Short-channel transistors susceptible to hot hole
  and electron injection into oxide layer
• Reliability risk
• Increases as Leff is reduced unless VDD is scaled

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Leakage Summary

• GIDL dominates

• DIBL dominates

• Weak inversion dominates

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Leakage Current Estimation

• Ignore diode junction leakage
• Subthreshold leakage increases exponentially with
  reduction of Vt
• Necessary transistor model elements
• Sub-zero VGS for nFET
• Super-zero VGS for pFET
• Body effect
• DIBL

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Subthreshold Current of MOSFET BSIM2 Model

• Cox gate oxide C/unit area
• m0 zero-bias mobility
• n subthreshold swing coefficient
• Vth0 zero-bias threshold voltage
• VS source voltage (above bulk voltage)
• g linearized body effect coefficient
• h DIBL coefficient

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Finding VDS for Transistor Stack

• Parallel off transistors VDS and VS same for
  both
• Series transistors leakages same through all
• Consider all nFETs turned off
• Equate top of stack transistor and 2nd transistor
  leakage currents
• Solve for VDS2 in terms of VDD
• Solve for VDSi in terms of VDSi-1

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Computing Pleak

• Get VDSi
• Use Equation 5.2 to get Isub
• Sum up
• For large circuit
• Determine pull-up and pull-down trees that are
  off
• Turned-on transistors treated as short circuits
• Ignore transistors parallel to turned-on
  transistors
• Use above method to get leakage power
• Calculate sensitivity to Vth

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Input Selection for Standby Mode

• Logic gate input vectors greatly affect leakage
  current
• Can apply low leakage current vector in standby
  mode
• Genetic algorithm (Chen et al.) to estimate
  standby leakage power

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Summary

• CMOS logic family greatly affects power
• Pass transistor logic on SOI is most promising
• Leakage current calculation in deep submicron
  transistors is important