ECE 425 VLSI Circuit Design

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ECE 425 - VLSI Circuit Design

• Lecture 7 - Combinational Logic Design
• February 16, 2004

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• Entry Exam Due Today
• Homework due Wednesday 2/18
• 2-2, 2-5, 2-6, , 2-7, 2-8, 2-9, 2-10, 2-13, 2-18
• Problem 2-13 hints
• Assume VDD / p-transistors in top half,
• Gnd / n-transistors in bottom half
• Reading
• Wolf 2.1-2.6, 3.1-3.4
• Office Hours
• MWF 1-2
• R 10-12

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Where we are...

• Last Time
• ASIC Design
• Standard Cells
• Gate Arrrays
• FPGAs
• Today
• Combinational Logic Design
• Static CMOS Delay, Noise Margin Power

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Review Boolean Algebra

• Axioms - basic properties assumed to be true
• (A1) X if X?1 (A1) X1 if X?0
• (A2) if (X0) then X1 (A2) if (X1) then
  X0
• (A3) 000 (A3) 111
• (A4) 111 (A4) 000
• (A5) 01100 (A5) 10011
• Axioms establish
• Possible values (0, 1)
• Definitions of operations AND (), OR (), NOT()

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Review Boolean Algebra (contd)

• Theorems useful properties proved from axioms
• Some example theorems
• (T1) X0X (T1) X1X Identities
• (T2) X11 (T2) X00 Null elements
• (T3) XXX (T3) XXX Idempotency
• (T4) (X)X Involution
• (T5) XX1 (T4) XX0 Complements
• (T6) XYYX (T6) XYYX Commutativity
• (T7) (XY)ZX(YZ) Associativity
• (T7) (XY)ZX(YZ)
• (T8) XYXZ X(YZ) Distributivity
• (T8) (XY)(XZ) XYZ

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Review Boolean Algebra (contd)

• More theorems
• (T9) XXYX (T9) X(XY)X Covering
• (T10) XYXYX Combining
• (T10) (XUY)(XY)X
• (T11) XY XZ YZ XY XZ Consensus
• (T11) (XY)(XZ)(YZ) (XY)(XZ)
• (T13) (XY) X Y DeMorgan
• (T13) (XY) X Y
• For more information
• Consult your logic design (ECE 211-212) notes, or
  
• See a logic design text, such as
• J. Wakerly, Digital Design, Principles and
  Practices 2nd. Ed., Prentice-Hall, 1994

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Logic Expressions

• Operators
• AND ab a b
• OR a b
• NAND a b
• XOR a Å b ab ab
• Literals - appearance of input variables
• unverted a
• inverted a'

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Completeness

• A set of logical functions is complete if we can
  generate every possible Boolean function using
  that set
• The set AND, OR, NOT is complete
• The set NAND is complete
• The set AND, OR is not complete

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Irredundancy

• A logical expression is irredundant if no literal
  can be removed from the expression without
  changings its value
• Redundant expressions
• ab a
• ab ab'
• Irredundant expressions
• ab' a'b
• a cd'

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Minimality

• A logic expression is minimal if no equivalent
  form has a higher cost (i.e., literal count)
• Minimality ? Irredundancy
• CAD tools are available to find the minimal (or
  near-minimal) form for
• Two level logic (AND/OR Sum of Products)
• Multilevel Logic (Arbitrary network of gates)

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Review - Complementary CMOS

• Pullup Network - drives output to VDD
• Pulldown Network - drives output to GND

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Complementary CMOS Notes

• Pullup, pulldown networks should NEVER conduct at
  same time!
• Pullup, pulldown networks are duals
• Parallel in pulldown implies serial in pullup
• Serial in pulldown implies parallel in pullup
• Gate Types
• Simple NAND, NOR, inverter
• And-Or-Invert (AOI)
• Or-And-Invert (OAI)

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Layout Considerations

• Metal lines required for Vdd!, Gnd!
• ndiff, pdiff must be separated by 10 lambda
• Transistor options
• horizontal or vertical diffusion lines
• Start with minimum-size transistors
• Increased width implies increased driving
  capability, but
• Do the analysis first to see if its necessary

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Layout Considerations (cont'd)

• Interconnect layers (use vias when necessary)
• Metal 1
• Metal 2
• Poly
• Diffusion
• Specify a well depending on process type
• Use substrate contacts to bias transistors
  prevent latchup

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Layout Example - NAND

• Compare to Fig 3-10, p. 122
• Differences from Magic
• Explicit contact cuts
• P-tub as well as N-tub
• Larger N-well
• Note transistor sizes
• Note substrate contacts

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Layout Example - NOR

• Compare to Fig 3-12, p. 123
• Differences from Magic
• Explicit contact cuts
• P-tub as well as N-tub
• Larger N-well
• Note transistor sizes
• Note substrate contacts

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Layout - Creating Wide Transistors

• Divide into multiple transistors
• Tie together sources, drains
• Compare to Fig 3-9, p. 121
• Missing but still needed substrate contacts

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Review - CMOS Gate Structure
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Inverter - DC Analysis
in
out
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Inverter DC Analysis - Continued
Note dependence on bn/bp Recall
Source N. Weste K. Eshraghian, Principles of
CMOS VLSI Design Addison Wesley, 1992
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Logic Levels Output

• Logic values are represented by a range of
  voltages
• Logic 1 between VOH and VDD (5V)
• Logic 0 between VOL and VSS (0V)
• Static CMOS Output levels
• VOH VDD (5V)
• VOL VSS Gnd (0V)

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Logic Levels Input

• Examine DC Input/Output Curve (Fig 3-15, p. 120)
• Pick points where slope -1 as VIL , VIH
• Rationale compare change in VIN , VOUT
• VIN lt VIL - small change in VIN causes small
  change in VOUT
• VIN gt VOUT - small change in VIN causes small
  change in VOUT
• VIN lt VIL lt VIH - small change in VIN causes
  large change in VOUT

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Logic Levels - Summary
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Noise Margin

• A measure of noise immunity
• Logic 1 NMH VOH - VIH
• Logic 0 NML VOL - VIL
• Important when noise is present
• Definition small random variations in voltage
• Dont want noise to affect circuit output

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Transistor Sizing and Noise Margin

• Changing beta (size) ratio changes VIH, VIL
• To balance noise margin
• Make bnbp gt Wp3.5Wn
• Actually, Wp2Wn is often good enough

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Gate Delay

• Consider an inverter with "step function" input
• Delay related to time to discharge / charge CL

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Simplifying Assumptions

• Assume transistors turn on/off instantaneously
• Model transistor as a switch, resistor in series
• Resistor approximates Vds/Id at different values
  of Vds
• (See Fig. 2-6, p. 45 Fig 3-17, p. 123, Fig. 3-18,
  p. 123)
• Use average of Vds/Id at
• middle of linear region Vlin 0.5(Vds - Vss -
  Vt)
• maximum of saturation region Vsat (Vds - Vss)

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Delay Calculation - Finding Rn
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Delay Calculation - Finding Rn
Table 3-1, p. 130 (0.5µm process, VDD5V) Rn
3.9k? Rp 14k?
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Calculating Rn, Rp
8.02k?
13.72k?
28.25k?
44.15k?
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Coming Up

• Body effect
• Power Consumption
• Power-speed product
• Parasitics and delay