Robust Memory Design Under Process Variations

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Robust Memory Design Under Process Variations

• Zheng Guo
• Professor Borivoje Nikolic
• University of California, Berkeley

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Problem Variations!

• Global
• Material properties of wafer, resists, etc.
• Lens aberration, flow turbulence, oven
  temperature, etc.
• Implant dose, diffusion time, focus, exposure
  energy, etc.
• Bhavnagarwala, 2004.
• Lg, W, oxide thickness, layer thickness, doping,
  etc.
• Local
• Line Edge Roughness (LER).
• Random dopant fluctuations.
• Statistical fluctuations in number and position
  of dopant atoms in the channel spatially
  uncorrelated.
• Discrete oxide thickness.

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SRAM Yield Limitations

• Read Stability
• Cell can flip due to increase in the 0 storage
  node above the trip voltage of the other inverter
  during a read.
• Hold Stability
• Data retention current not able to compensate the
  leakage currents.
• Access Time
• Time required to produce a pre-specified ?V
  between the bit lines is higher than the maximum
  tolerable limit.
• Write Stability
• 1 Storage node may not be reduced below the
  trip point of the other inverter before WL is
  discharged.

Mukhopadhyay et al, 2004
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Read Stability
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Hold Stability

• Similar to Read Stability analysis without access
  transistor.
• PR must provide enough leakage to compensate for
  leakage in NMOS pull-down and access transistors.

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Read Access

• Must provide ?V between the bit lines within
  maximum tolerable time limit.
• Limited to floating bit-line implementation with
  voltage sensing amplifiers.
• Sum BL currents and integrate.

Mukhopadhyay et al, 2004
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Write Stability
Mukhopadhyay et al, 2004
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Memory Design as Robust Optimization

• Robust optimization under yield constraints.
• Metrics and yield constraints in memory design
  can be expressed as polynomial equations.
• Problem minimization of a scalar function under
  certain yield constraints.
• Scalar function can represent area/power/leakage
  (or a mix) and can be expressed as a function of
  VDD, (W/L) ratios, WL/BL voltages, cell per
  column/row, etc.
• Yield constraints can be represented as

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Double-gate MOSFET

• Back-gate biasing of a thin-body MOSFET remains
  effective for dynamic control of Vt with
  transistor scaling, and can provide improved
  control of short-channel effects as well.
• Collaborate work with Sriram B., Radu Z., and
  Prof. T. J. King.

• Back-gated (BG) MOSFET
• Independent front and back gates
• One switching gate and Vth control gate

Double-gated (DG) MOSFET
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Conventional 6T SRAM Cell

• Double-Gated (DG) FinFET Architecture.
• FinFET channel surface along (110) plane.
• High Threshold devices used to suppress leakage.
• NMOS work-function used for PMOS devices.
• PMOS work-function used for NMOS devices.
• SNM during read 210mV.

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6T SRAM Cell with Rotation
6.6um X 8um

• Double-Gated (DG) FinFET Architecture with
  Rotation.
• Channel surface along (110) plane for access and
  PMOS load devices.
• Channel surface along (100) plane for NMOS
  pull-down devices to increase ß-ratio.
• High Threshold devices used to suppress leakage.
• NMOS work-function used for PMOS devices.
• PMOS work-function used for NMOS devices.
• SNM during read 230mV.

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6T SRAM Cell with Feed-back

• Double-Gated (DG) NMOS pull-down and PMOS load
  devices.
• Back-Gated (BG) NMOS access devices to
  dynamically increase ß-ratio.
• FinFET Channel surface along (110) plane.
• High Threshold devices used to suppress leakage.
• NMOS work-function used for PMOS devices.
• PMOS work-function used for NMOS devices.
• SNM during read 300mV.
• Area penalty 19
• Motivation from Yamaoka, Hitachi, 2004

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4T SRAM Cell Design
Yamaoka, Hitachi, 2004

• Data retention leakage current usually need to be
  at least 1000xIleakage to compensate for the
  widely fluctuating leakage current.
• Data retention leakage current flows on both
  sides but only needs to flow in one side for data
  retention.

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4T SRAM Cell with Feed-back

• Double-Gated (DG) NMOS pull-down devices.
• Back-Gated (BG) PMOS access devices to
  dynamically increase compensation current and
  ß-ratio.
• FinFET Channel surface along (110) plane.
• NMOS work-function used for PMOS devices high
  threshold.
• NMOS work-function used for NMOS devices
  nominal threshold.
• SNM during read 310mV.
• Area savings 36 compared to 6T BG and 24
  compared to 6T DG.

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4T SRAM Write Issue

• Directions of ICOMPENSATION may reverse while
  writing to a neighboring cell (cell sharing same
  bit-lines).
• PMOS devices can only pull 1 storage node down
  to Vtp.
• Bit is kept as long as 1 storage node stays
  above Vtn.
• Problem alleviated by employ high-Vtp PMOS
  devices.
• NMOS work-function used for PMOS devices high
  threshold.
• NMOS work-function used for NMOS devices
  nominal threshold.
• Write margin improved by increasing PMOS drive
  current.
• Word-line swing increased -200mV to 1V.

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Statistical Variations

• Statistical variations in TSi and LG.
• 3sLG 3sTSi 10 LG.
• 4T cell design shows superior SNM with tighter
  distribution than 6T cell designs.

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SRAM Layouts
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Conclusion

• Cell stability analysis was presented.
• Memory design as robust optimization was
  introduced.
• SRAM designs using FinFETs were investigated.
• The benefits of using dynamic feedback in
  FinFET-based SRAM cell designs were demonstrated.
• The 4T design with dynamic feedback was shown to
  achieve larger noise margins than 6T SRAM designs
  and is therefore attractive for high-density
  memory applications.