INSTRUCTION CYCLE

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CHAPTER 4

• INSTRUCTION CYCLE

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Chapter Outline

• Introduction
• Fetch cycle
• Execute cycle
• Interrupts

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4.1 Introduction

• Instruction cycle refers to the processing
  performed by a CPU to execute a single
  instruction
• Each basic cycle is made up of FETCH and EXECUTE
  cycle

Basic Instruction Cycle
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Instruction Cycle State Diagram, without Interrupt
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• The states can be described as below-
• Instruction address calculation (iac)
• determine the address of the next instruction
• Instruction fetch (if)
• Read instruction from its memory location into
  the processor
• Instruction operating decoding (iod)
• Analyse instruction to determine type of
  operation to be performed and operands to be used
• Operand address calculation (oac)
• Determine the address of the operand

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• Operand fetch (of)
• Fetch operand from memory or read it in from I/O
• Data operation (do)
• Perform the operation indicated in the
  instruction
• Operand store (os)
• Write the result into memory or out to I/O

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4.2 Fetch Cycle

• This cycle involves fetching of instruction from
  memory by the CPU
• 4 registers are used

• Program Counter (PC)
• Memory Address Register(MAR)  
• Memory Buffer Register (MBR)  
• Instruction Register (IR)

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• The following steps are performed
• PC holds address of the next instruction to be
  fetched
• Processor fetches instruction from memory
  location pointed to by PC
• Increment PC unless told otherwise
• Instruction is loaded into IR
• Processor interprets instruction and performs the
  required action

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4.3 Execute Cycle

• Processor-memory
• Data transfer between CPU and MM
• Processor I/O
• Data transfer between CPU and I/O modules
• Data Processing
• Some arithmetic or logical operation on data
• Control
• Alteration of sequence of operations eg. JUMP
• Combination of the above

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• An example

Example of program execution
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4.4 Interrupts

• The mechanism by which other system modules may
  interrupt the normal processing of the CPU
• These devices are 1-10 orders of magnitude slower
  than the CPU
• There are 3 different types of interrupts
• Internal due to invalid data / instructions
• External normally from I/O devices
• Software used by the OS

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• Interrupts let the CPU
• execute its normal instruction sequence and
• pause to service the external devices
• ONLY when they signal that they
• are ready for the CPUs attention
• The processor and OS are responsible for
• recognizing an interrupt,
• suspending the user program,
• servicing the interrupt and then
• resuming the user program

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• Interrupts are processed in an interrupt cycle
  within the overall instruction cycle
• At the end of an instruction cycle, check to see
  if any interrupts are pending
• If there arent any,proceed with the next
  instruction

• If there are interrupts
• Suspend execution of the program and save its
  state
• Jump to ISR and resume normal instruction cycle
• When ISR is completed, restore the state of the
  program and resume its operation

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Instruction Cycle State Diagram, with Interrupt
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Transfer of control via interrupt
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• A typical system can support multiple interrupts
• If more than 1 interrupts occur at the same
  time-
• Systems prioritize the various interrupts
• At the start of the interrupt cycle, the highest
  priority pending interrupt will be serviced
• Remaining interrupt requests will be serviced in
  turn

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• If an interrupt occur while an ISR is being
  executed then
• Ignore the second interrupt until the ISR
  completes e.g. MC68HC11 controller
• Recognize and service the interrupt only if it
  has a higher priority than the one currently
  being serviced e.g. 8085

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Sequential Interrupt Processing
Nested Interrupt Processing
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Program Flow of Control without and with Interrupt
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Chapter Exercises

• Design issues with multiple modules and thus
  multiple interrupts..
• How does the CPU determine which device caused
  the interrupt?
• If multiple interrupts occur at the same time,
  which is processed first?