Circuit Switch Design Principles

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Chapter 2

• Circuit Switch Design Principles

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Fig. 2.1. An N x N switch used to interconnect N
inputs and N outputs
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Fig. 2.2. Bar and cross states of 2 x 2 switching
elements
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Fig. 2.3. (a) Crossbar switch
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Fig. 2.3. (b) banyan switch
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• Nonblocking Properties

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Fig. 2.4. (a) A 4 x 4 rearrangeably nonblocking
switch
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Connection cannot be set up between input 4 and
output 1

• Fig. 2.4. (b) a connection request from input 4
  to output 1 is blocked

Connection can now be set up between input 4 and
output 1

• Fig. 2.4. (c) Same connection request can be
  satisfied by rearranging
• the existing connection from
  input 2 to output 2

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• Two states corresponding to the same mapping

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• Complexity of nonblocking switches
• How to build large switch from smaller switches?

Problems with two-stage networks
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Fig. 2.5. (a) An example of one-to-one mapping
from input to output
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Fig. 2.5. (b) Number of crosspoints needed for
nonblocking switch
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Fig. 2.6. A three-stage clos switch architecture
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Fig. 2.7. An example of blocking in a three-stage
switch
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Fig. 2.8. The connection matrix of the
three-stage network
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• Conditions of a Legitimate connection Matrix

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• Strictly nonblocking

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• Rearrangeably nonblocking

Rearrangement Substituting symbols in
connection matrix such that 1.) Matrix remains
legitimate 2.) An unused symbol in row A and
column B can be found
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Fig. 2.9. (a) A chain of C and D originating from
B
Fig. 2.9. (b) Physical connections corresponding
to the chain
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• Fig. 2.10. Illustration showing loops in chains
  are not
• permitted in legitimate
  connection matrix

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• Fig. 2.11. (a) Rearrangement of the chain in Fig.
  2.9.

• Fig. 2.11. (b) Corresponding rearrangement of
  connections

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• Fig. 2.12. (a) Two chains, one originates from B,
  one from A

• Fig. 2.12. (b) Illustration that the two chains
  cannot
• be connected

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• How many rearrangements?
• A new row/column is covered each time a point
  is included
• (r1 r3 2) other rows and columns
• At most (r1 r3 1) rearrangements (loose)

• Basic consider two chains, one originates from
  row A,
• one from column B
• Choose the shorter chain for rearrangement
• A composite move a move in chain 1 with a move
  in chain 2
• At most r1 2 moves before all rows
  exhausted
• At most r3 2 moves before all columns
  exhausted

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• Fig. 2.13. Recursive decomposition of a
  rearrangeably
• nonblocking network

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• Number of 2x2 elements in Benes Network

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• Fig. 2.13(1). Illustration of a looping
  connection
• setup algorithm

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Fig. 2.14. An 8x8 Benes Network
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• Properties of Benes Network
• 1.) Unique path property of underlying baseline
  and reverse baseline networks
• 2.) Binary tree to middle-stage nodes
• an input can reach 2j-1 nodes at stage j, j
  lt log2N
• 3.) Reachability of nodes in baseline/reverse
  baseline networks
• A node in stage i can be reached by 2i inputs
  and
• can reach 2n-j1 outputs
• 4.) Middles nodes blocked by an existing path

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• Fig. 2.15. Cantor network

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• Cantor Network is SNB
• 1.) Let m be of Benes Network required
• 2.) Worst case all other N-1 inputs/outputs busy
• ? there are (N-1) paths to middle nodes
• 3.) One path meets the binary tree at stage 1
• Two paths at stage 2

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• 4.) A node in stage i blocks

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Fig. 2.16. Binary tree extended from an input to
all middle-stage nodes
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Fig. 2.17. Direct time slot interchange using
random access memory (switching
in the time domain)
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Fig. 2.18. Performing time slot interchange
using space-division switch
D E M U X
D E M U X
Space division switch
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Fig. 2.19. A time-space-time switch
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Fig. 2.20 A time-space time switch
( i, j ) data on input i at time slot j
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Fig. 2.21. Equivalent of time-space-time
switching and three-stage space
switching
A(1,1)
D(2,1)
CBA
BAC
EDC
CED
B(1,2)
E(2,2)
C(1,3)
C(1,3)
D(2,1)
A(1,1)
FED
EDF
HAL
LHA
E(2,2)
H(3,2)
F(2,3)
L(3,3)
G(3,1)
G(3,1)
LHG
GBF
HGL
BGF
H(3,2)
B(1,2)
L(3,3)
F(2,3)
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Fig. 2.22. Input-output mapping changes from slot
to slot in space-division switch
in time-space-time switching
( i, j ) data on input i at time slot j
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Fig. 2.23. Equivalent of time-space-time
switching and three-stage space
switching
Module (i) corresponds to time slot i
of space-division switch in time-space-time switch
Module (i) corresponds to output TSI (i)
in time-space-time switch
Module (i) corresponds to input TSI (i)
in time-space-time switch