ECE 406

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ECE 406 Design of Complex Digital Systems
Lecture 13 MemAccess Block
Spring 2007 W. Rhett Davis NC State
University with significant material from Paul
Franzon, Bill Allen, Xun Liu
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MemAccess

• Receives Address to be read/written from Execute
  block
• Receives Data to be written from Decode block
• Master of the shared Memory bus during the Read
  Memory, Write Memory, and Indirect Address
  Read states.
• Provides Data read from Memory to Writeback block

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Detail of Memory Bus
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MemAccess Signals

• What is meant by the M_Data signal? Why does it
  come from the Decode block?
• What is meant by the M_Addr signal? Why does it
  come from the Execute block?
• What is meant by the memout signal?

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MemAccess States
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Read Memory State LD, LDR

• Determine the Memory Bus Signals
• rd
• addr
• din

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Write Memory State ST, STR

• Determine the Memory Bus Signals
• rd
• addr
• din

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Read Indirect Address State LDI, STI

• Determine the Memory Bus Signals
• rd
• addr
• din

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Example LDI

• Location of Indirect Address 16h300A
• Indirect Address 16h3010
• Value Stored at Indirect Address 16h1234

Note that dout is the same as addr
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Example STI

• Location of Indirect Address 16h300A
• Indirect Address 16h3010
• Value to be Stored at Indirect Address 16h1234

Note that dout is the same as addr
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Read Indirect Address State

• During this state, what will dout be set to?
• What needs to happen to this value on the next
  cycle?
• How can we ensure that this happens?

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Read/Write Memory States Revisited

• Read State Memory Bus Signals
• rd
• addr
• din

• Write State Memory Bus Signals
• rd
• addr
• din

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Verilog Code for MemAccess

• Read Memory State
• if(M_Control0) addrltM_Addr else
  addrltdout
• dinlt16'h0 // dont care
• rdlt1'b1
• Read Indirect Address State
• addrltM_Addr
• dinlt16'h0 // dont care
• rdlt1'b1

• Write Memory State
• if(M_Control0) addrltM_Addr else
  addrltdout
• dinltM_Data
• rdlt1'b0
• All Other States
• addrlt16'hz
• dinlt16'h0 // dont care
• rdlt1'bz

Remember that this is combinational logic!
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Complete the Table

Operation mode M_Control
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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What about memout?

• memout needs to present the value read from
  memory to the Writeback block.
• Theres really no reason why it cant just be
  connected to dout permanently (with an assign
  statement).
• assign memout dout