ECE 406

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ECE 406 Design of Complex Digital Systems
Lecture 12 Intro to the LC-3
Micro-architecture
Spring 2007 W. Rhett Davis NC State
University with significant material from Paul
Franzon, Bill Allen, Xun Liu
2
Announcements

• Project 1 Posted
• Bring Lecture 11 slides and Project 1 Assignment
  to lecture every day

3
Todays Lecture

• Block-Diagram of the LC3
• LC3 Controller State Machine
• Control Signals
• Controller
• Fetch
• Execute

4
Microarchitecture

• The von Neumann Model
• Memory
• Processor
• Input
• Output
• Control

memory
input
output
processor
control
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What Blocks Do We Need?

• Instructions
• ADD
• AND
• NOT
• BRx
• JMP/RET
• JSR
• JSRR
• LD
• ST
• LDR
• STR
• LDI
• STI

• ALU
• Register File
• Program Counter
• Status Register
• Instruction Register
• Logic to direct operands to/from ALU
• Logic to interface to Memory

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Conventions

• Control signals are omitted for simplicity
• Makes the diagram easier to read
• Usually far fewer control signals than data
  signals
• Wire bundles
• A set of nets going from one block to another is
  represented as
• When a set of nets contains signals that go in
  both directions (both input and output for a
  block), we use
• A set of nets on a shared bus (a bus with
  multiple drivers) is represented as
• If a block only reads or writes one signal on a
  shared bus, we use

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Simplified LC3 Microarchitecture
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Detail of Memory Bus
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Controller

• Maintains the master state-machine for the system
• Distributes this state to the rest of the system
  (not shown)

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Fetch

• Maintains the program counter (PC) for the system
• Communicates with Memory to make sure instruction
  is made available to Decode block
• Master of the shared Memory bus during the all
  states but the Read Memory, Write Memory, and
  Indirect Address Read states.
• Receives the next address from the Execute block
  (if a branch is taken)

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Decode

• Maintains the Register File (R0R7) for the
  system
• Maintains Instruction Register (IR) and
  Processor Status Register (PSR) which includes
  N, Z, P
• Receives instruction word from Main Memory
• Provides operands to Execute and MemAccess blocks
• Receives the value to write-back to the RegFile
  from the Writeback block
• Decodes every instruction and provides control
  signals to most blocks (not shown)

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Execute

• Directs operands from the Decode block to the
  Arithmetic Logic Unit (ALU)
• Sends result to the Writeback block (for storage
  in Register File), or Fetch block (with the next
  address on a branch)

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MemAccess

• Receives Address to be read/written from Execute
  block
• Receives Data to be written from Decode block
• Master of the shared Memory bus during the Read
  Memory, Write Memory, and Indirect Address
  Read states.
• Provides Data read from Memory to Writeback block

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Writeback

• Decides which value will be written back to the
  Register file
• Receives output of ALU from Execute Block
• Receives contents of MDR from MemAccess Block
• Sends result to Decode Block for storage in
  Register File

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Todays Lecture

• Block-Diagram of the LC3
• LC3 Controller State Machine
• Control Signals
• Controller
• Fetch
• Execute

16
Simplified State Machine
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Execution of ADD/AND/NOT

1. Fetch Unit loads instruction from memory
2. Decode Unit determines the operands
3. Execute Unit applies operands to ALU
4. Result stored in Register File
5. PC incremented

1
2
5
3
4
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Execution of BRx/JMP/RET

1. Fetch
2. Decode
3. Execute computes new PC
4. PC updated

1
2
4
3
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Execution of JSR/JSRR

1. Fetch
2. Decode
3. Execute computes new PC
4. PC stored in R7
5. PC updated

1
2
5
3
4
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Execution of LD/LDR

1. Fetch
2. Decode
3. Execute Unit computes address
4. MemAccess Unit reads Memory
5. Write to Register File
6. PC incremented

1
2
6
3
4
5
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Execution of ST/STR

1. Fetch
2. Decode
3. Execute Unit computes address
4. MemAccess Unit writes Memory
5. Update PC

1
2
5
3
4
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Execution of LDI

1. Fetch
2. Decode
3. Compute address
4. Read Memory for Indirect Address
5. Read Memory
6. Update Register File
7. PC incremented

1
2
7
3
4
5
6
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Execution of STI

1. Fetch
2. Decode
3. Compute address
4. Read Memory for Indirect Address
5. Write to Memory
6. Update PC

1
2
6
3
4
5
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Execution of LEA

1. Fetch
2. Decode
3. Compute address
4. Update Register File
5. Update PC

1
2
5
3
4
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How Good Is Our Micro-architecture?

• What is the average number of cycles per
  instruction
• Modern microprocessors get this number close to
  1.0 for scalar machines and less than 1.0 for
  super-scalar and VLIW machines.
• Take courses like ECE 463 ECE 464 to learn how.

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Todays Lecture

• Block-Diagram of the LC3
• LC3 Controller State Machine
• Control Signals
• Controller
• Fetch
• Execute

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Control Signal Tables

• It helps greatly in the debugging of the LC-3
  System to have completed tables that give the
  values of various control signals, depending on
  the instruction that is being executed.
• In this section, we will begin to fill out these
  tables.
• The instruction-set specification is needed to
  complete these tables, and is included here for
  convenience.

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ALU Operations
15 12 11 9 8 6 5 4
3 2 0

• ADD
• AND
• NOT

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Control Instructions
15 12 11 9 8 6 5 4
3 2 0

• BR
• JMP
• JSR
• JSRR
• RET
• RTI
• TRAP

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Load/Store Instructions
15 12 11 9 8 6 5 4
3 2 0

• LD
• LDR
• LDI
• LEA
• ST
• STR
• STI

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Complete the Table
C_Control C_Control C_Control C_Control
Operation mode Instr. Type Store PC Mem. Access Mode load
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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Fetch Module Inputs Outputs

• Input Signals
• clock global system clock.
• reset when high, the PC should be synchronously
  set to x3000
• state the state from the Controller block.
• taddr150 the next value of the PC if a
  branch is taken.
• br_taken signal to indicate that a branch is
  taken.
• Output Signals
• rd signal to indicate to the Memory that a read
  is to be performed, rather than a write. This
  signals should be high-impedence during the Read
  Memory, Write Memory, and Indirect Address
  Read states, because the MemAccess block will
  drive the shared bus during these cycles. In all
  other states, this signal should be high.
• pc the current value of the program counter,
  but should be high-impedence at the same times
  that the rd signal is high-impedence.
• npc should always be PC1

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Fetch Block Sketch
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Complete the Table

Operation mode br_taken
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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Execute Block Sketch
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Complete the Table
E_Control E_Control E_Control E_Control E_Control
Operation mode ALU Op Sel ALU Op Sel PC Sel 1 PC Sel 2 OP 2 Sel
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI