ECE 406

1
ECE 406 Design of Complex Digital Systems
Lecture 2 Introduction to Verilog Syntax
Spring 2007 W. Rhett Davis NC State
University with significant material from Paul
Franzon, Bill Allen, Xun Liu
2
Summary of Last Lecture

• Explain the differences between the following
  terms
• Schematic vs. Block Diagram
• Port vs. Net
• Symbol vs. Instance
• System vs. Module
• HDL vs. RTL

3
Todays Lecture

• Verilog Introduction
• Conventions, Identifiers, Numbers, Operators
• Data Types
• Modules
• Test Benches

4
History of Verilog

• 1984 Developed by Gateway Design Automation
• 1995 Became an IEEE Standard (IEEE 1364-1995)
• 2001 Revised (IEEE 1364-2001)
• 2003 Accelera released the System Verilog 3.1
  specification
• Well use both the IEEE 1364-1995 and IEEE
  1364-2001 versions of the language.(Either will
  be accepted on your assignments).

5
Comparison of HDLs

• Verilog
• Most commonly used HDL in USA
• Based on the C programming language
• Least verbose
• Fastest simulation
• VHDL
• Used by US Government, Europe, ASIA
• Based on the ADA programming language
• More general than Verilog
• SystemC
• Emerging Standard, used more for Electronic
  System Level (ESL) Descriptions
• C class library that mimics VHDL, plus allows
  greater abstraction
• Allows co-simulation of Hardware and Software

6
Todays Lecture

• Verilog Introduction
• Conventions, Identifiers, Numbers, Operators
• Data Types
• Modules
• Test Benches

7
Example Data Selector
Route input data to one of two outputs.
Specification When a new data word arrives at
the input, the module inspects the state of the
most significant bit and routes the data to
output A if the bit is true and to B if the bit
is false. The last value sent to either output
is retained until replaced.
8
Example Stimulus

• How to describe the module?
• How to describe the stimulus?

9
Verilog Language Conventions

• Case sensitive
• Whitespace ignored (except in strings)
• Comments (just like C and Java)
• Single Linea b c // The rest of this line
  is a comment
• Multi-Line (cannot be nested)/ This is a
  multiple linecomment/

10
Identifiers

• Can contain
• Letters (a-z,A-Z)
• Digits (0-9)
• Underscore (_)
• Dollar-sign ()
• Must start with a letter
• Except for weird things like \reset
• Cannot be a keyword (see Sutherland, section 3.0
  for a full list)

11
Operators

• Unary - single operand
• in
• Binary - two operands
• in1 in2
• Ternary - three operands
• select ? in1 in2
• Nearly all Verilog statements end with a
  semicolon (dont forget it on your homework)

12
Values
Sized numbers ltsizegtltbase formatgtltvaluegt
ltsizegt specifies number of bits in number (in
decimal) ltbase formatgt decimal (d, D)
hexadecimal (h, H)
binary (b, B) octal (o, O) ltvaluegt
digits (in base format) of the numeric value

• Write the following
• Binary 100111, 6 bits
• Hex 7FFE, 16 bits
• Decimal 133, 8 bits
• Omitting ltsizegt gives an unsized value (32 bits)

13
Special Values
Language conventions Numbers Values
In addition to normal numeric values, Verilog
provides two special values, x and z.
x denotes an unknown or undefined value. unknown
by the simulator
z denotes a high impedance value isolated
from from other regions of the circuit by open
switches

• Write the following
• 16-bit hex, low order 4 bits unknown
• 8-bit binary, high order 2 bits unknown
• 8-bit value, all bits high impedance

14
Physical Meaning of Values
Draw a circuit to represent the following values
x
0 and 1
15
Physical Meaning of Values
Draw a circuit to represent the following values
z
16
Values Special Cases
Zero fill / extension If a numeric value does
not contain enough digits to fill the specified
number of bits, the high order bits are filled
with zeros. If the most significant bit
specified is an x or z, the x/z is left extended
to fill the bit field.
16h39 ? 8hz ?
Negative numbers Specified by preceding the
ltsizegt with a minus (negative) symbol. Values
will be stored as the twos complement of the
given value.
17
Verilog 2001 Syntax

• Signed Values ltsizegtsltbase formatgtltvaluegt
• The s denotes that a value is signed (all
  other values are assumed unsigned)
• This does not change the value, but it does
  change how certain operators deal with the value
  (namely, whether or not it will be sign-extended)
• Examples
• 4hF 1111 in binary
• 4shF 1111 in binary (but will sometimes be
  interpreted as -1)

18
Example Stimulus

• How would you write the values for Data and here?
  (assume Data is 4 bits)

19
Todays Lecture

• Verilog Introduction
• Conventions, Identifiers, Numbers, Operators
• Data Types
• Modules
• Test Benches

20
Net Variables
Nets represent connections between hardware
components.
Nets are usually declared by the keyword wire.
wire d // declare output as net d. wire b,
c // declare two wires in same statement
21
Register Variables
Registers are variables that can hold a value.
not necessarily the same as a hardware register
Registers can be assigned values multiple times
during a simulation, but Nets can be assigned
only at the beginning of a simulation.
Would you use a Net or a Register variable for
the Data and here signals in the Data Selector
example?
Registers are declared by the keyword reg. The
default value for a reg data type is x.
reg start // declares register start reg
reset, clock // declares registers reset clock
22
Bitvectors
Bitvectors can be specified by declaring the
range of bit numbers with the variable name. The
form of the declaration is lthighgt ltlowgt
ltvariablegt or ltlowgt lthighgt ltvariablegt
// declare 8-bit data named BYTE // declare
16-bit register named INFO // declare 12-bit
register named DATA

• Left bit is considered the most significant
• By convention, use lthighgtltlowgt

23
Specifying Parts of Vectors
Given vector declarations, it is possible to
reference parts of a register (down to a single
bit). The format of the reference follows the
pattern ltvectorgt ltbit rangegt.
// bit 5 of INFO // bits 11-8 of INFO (bits
11-8) // least significant byte of DATA
24
Other Types

• Integer
• Real
• Time (accessed w/ system function time)
• Rarely used in the description of a hardware
  module but are frequently useful in the Test
  Bench.
• See Sutherland, section 7.0 for details

25
Arrays
Arrays can be declared for both scalar and vector
data. An array is simply an ordered group of
elements. All arrays are single dimensioned in
Verilog. Arrays are declared with the
syntax ltarray_namegtltcell_rangegt
or ltbit_rangegtltarray_namegtltcell_rangegt
reg bool 310 // 32 1-bit boolean register
values integer count 09 // array of 10 count
variables reg 70 PID 05 // array of 6 bytes
26
Memories
Memories are defined by the syntax ltbit_rangegt
ltnamegt ltaddressing_rangegt
reg bitmem 01023 // 1K x 1 (bit) memory reg
70 MEM 016383 // 16K x 8 or 16K bytes
Note that the addressing range is usually
specified as ltlow_addressgt lthigh_addressgt and
for physical reasons, the address range starts at
0.
27
Symbolic Constants (Parameters)
The parameter keyword allows definition of a
symbolic label with a constant value. Anytime
that label is used in the Verilog code, it is
replaced with its constant value.
parameter size 16 // defines a constant
called // size with a value of 16
For example, if size is defined with a value of
16, the memory declaration reg size-1 0
MEM 0 4095 gives the same result as
writing reg 150 MEM 04095
28
Verilog 2001 Syntax

• Signed Variables can be declared with the
  keyword signed
• As with signed values, declaring a variable as
  signed does not change its value, but rather how
  certain operators deal with the value (namely,
  whether or not it will be sign-extended)

reg signed 70 mybyte wire signed 50 myvar
29
Todays Lecture

• Verilog Introduction
• Conventions, Identifiers, Numbers, Operators
• Data Types
• Modules
• Test Benches

30
Module Descriptions in Verilog
The Verilog description of a digital module
follows a prescribed structure as follows

• Header
• Parameters
• Port declarations
• Variable declarations
• Instantiation of lower-level modules
• Functionality description
• - Gate-level
• - Data Flow
• - Behavioral
• Terminator

Lets write a module description for the Data
Selector
31
Header Port Declarations
Module header names the module and lists ports.
module ltnamegt ( ltport listgt )

Port declarations specify the input and output
port characteristics. (like variable
declarations, but use the keywords input and
output)

32
Variable Declarations
Variable declarations specify modules nets
registers.
reg 150 A, B // A B are 16-bit
registers wire 150 Data, A_data, B_data wire
here, new_A, new_B
Note The wire declarations could be omitted
since port declarations imply the associated nets.
33
Verilog 2001 Syntax

• Verilog 2001 allows port declarations within the
  port-list

1995 Syntax
2001 Syntax

• module data_selector (Data, here, A_data,
  new_A, B_data, new_B)
• input 150 Data
• input here
• output 150 A_data, B_data
• output new_A, new_B

• module data_selector ( input 150 Data,
• input here,
• output 150 A_data, B_data,
• output new_A, new_B )

34
Instantiation, Functionality, Terminator
Instantiation of lower-level modules creates a
unique named instance for each of the low-level
modules. ltmodule_namegtltinstance namegt
(ltport_listgt)
Functionality description specifies the internal
organization and operation of the module. There
are three levels of abstraction that will be
studied
Terminator marks the end of the Verilog module
description. It is simply endmodule (without a
trailing semicolon).
35
Data Selectors Module Description
1995 Syntax
module data_selector (Data, here, A_data,
new_A, B_data, new_B)
input 150 Data input here output 150
A_data, B_data output new_A, new_B
reg 150 A, B wire 150 DATA, A_data,
B_data // these 2 lines can wire here, new_A,
new_B // be omitted
// No modules to instantiate for this design
// Description of functionality would go here
endmodule
36
Data Selectors Module Description
2001 Syntax

• module data_selector (input 150 Data, input
  here, output 150 A_data, B_data, output
  new_A, new_B) reg 150 A, B// No modules
  to instantiate for this design
• // Description of functionality would go here
• endmodule

37
Todays Lecture

• Verilog Introduction
• Conventions, Identifiers, Numbers, Operators
• Data Types
• Modules
• Test Benches

38
Creating the Stimulus

• We know how to describe the Data-Selector, but
  how do we describe its stimulus?
• Need to specify a behavior that has a beginning
  and an end.

39
Initial Blocks

• Use an initial block to specify a behavior for a
  module that executes once at the beginning of the
  simulation. initial begin myvar
  4d9 myvar 4d7 end
• begin and end are needed only if there is more
  than one statement in the initial block (like
  and in C)
• Looks a bit like Pascal and Ada
• Note that there is no semicolon after initial,
  begin, end
• In the example above, is myvar declared as wire
  or reg?

40
Displaying Values

• Use the system task display to print out values
• display is like printf() in C (see Sutherland,
  section 18.0 for details)module
  helloinitial display(Hello
  World!\n)endmodule //hello

41
Representation of Stimulus
module test reg 30 Data initial begin
Data 4'h2 display("Data
h",Data) Data 4'hA
display("Data h",Data) Data 4'h7
display("Data h",Data)
end endmodule //test
42
Summary

• What characters are allowed in identifiers?
• What kinds of circuits would generate the values
  0, 1, x, and z?
• What is the difference between wire and reg
  variables?
• What parts of the module description do you need
  to create a test-bench?

43
Homework 1 Tips

• Problem 2 (a) and (b)
• Please convert to binary manually
• Problem 7
• See Sutherland, section 19.0 for an example of
  the define compiler directive