RISC

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RISC

• By Omar Hernandez
• CS147

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Types of CPUs

• CISC

• RISC

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Types of CPUs

• Complex
• Instruction
• Set
• Computers

• Reduced
• Instruction
• Set
• Computers

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CISC

• Have large instruction sets that are close to
  higher language structures
• Examples of CISC
• Intels Pentium- class CPUs
• Motorola 68000 CPUs

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RISC

• Reduced
• Instruction
• Set
• Computing

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RISC

• Instruction set for RISC processors are
• Simple
• Pure Assembly language dedicated to the design of
  the CPU

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RISC Features

• Fixed length Instructions
• Limited Loading and Storing Instructions Access
  Memory
• Fewer Addressing Modes
• Instruction Pipeline
• Large Number of Registers
• Hardwired Control Unit

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RISC Features (Contd)

• Delayed Loads and Branches
• Speculative Execution of Instructions
• Optimizing Compiler
• Separate Instruction and Data Streams

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RISC Instruction Sets

• In general have only up to 100 instructions in
  their set
• Each instruction is capable of being executed in
  a single clock cycle

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RISC Instruction Sets (Contd)

• Basic Instructions include
• Data move (load, store, register move)
• Arithmetic
• Logic
• Shift
• Branch (jumps)

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RISC Instruction Sets (Contd)

• RISC CPUs operate usually on two data types
• Integer
• Floating point
• Using different precisions or numbers of bits
  within a given data type
• Using these basic data types, you can program
  into more complex data types

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RISC Instruction Sets (Contd)

• RISC CPUs use different instruction formats
• Every instruction must have same amount of bits
  regardless of format
• CPU must be able to access each instruction code
  in a single memory-read operation in order to
  facilitate pipelining

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RISC Instruction Sets (Contd)

• Instruction set usually has different types of
  load and store due to bit alignment using from
• 8 bit
• 16 bit
• 32 bit
• Etc.

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RISC Instruction Sets (Contd)

• Addressing modes all depend on clock cycle
• Without it you would have to redesign pipeling
  used to process instructions

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RISC Instruction Sets (Contd)

• RISC II CPUs have
• 3 primary memory addressing modes
• Indexed address mode
• Register indirect address mode
• Contain a pseudoregister R0 thats always zero

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RISC Performance

• RISC uses two techniques to improve performance
• Instruction Pipeline
• Register Window Renaming

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RISC Performance (Contd)

• Instruction Pipeline
• Breaks down fetch-decode-execute process into
  several instructions in parallel
• Pipeline allows one instruction per clock cycle

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Instruction Pipeline
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Instruction Pipeline (Contd)
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Instruction Pipeline (Contd)
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Instruction Pipeline (Contd)
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Instruction Pipeline (Contd)

• Speedup is the ratio of time needed to process n
  instructions using nonpipelined control unit to
  the time needed using a pipelined control unit
  with the following formula

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Instruction Pipeline (Contd)

• is time needed to process 1 instruction using
  a nonpipelined control unit
• is number of stages in pipeline
• is clock period of the pipeline
• Example

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Instruction Pipeline Requirements

• RISC CPU must include cache memory that is at
  least as fast as the pipeline
• Cache must separate instructions and data to
  avoid memory conflicts from stages of pipeline
• Compiler has to be optimized to reorder
  instructions in order to avoid problems with
  branch instructions

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Register Windowing Renaming

• Takes advantage of large amounts of registers
  that RISC CPUs have
• Producing more hits to register than memory
• Thus producing faster CPU performance

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Types of registers

• Global register always accessible
• Windowed register a subset accessible at any
  specific time

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MIPS register organization
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Register Renaming

• Makes use of any group of register with pointers
• Doesnt follow a register convention which
  assigns registers to a certain task

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Instruction Pipeline Conflicts

• Data Conflicts
• Software fixes
• No-op insertion
• Instruction reordering
• Hardware fix
• Stall insertion
• Data forwarding
• Branch Conflicts

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Data Conflicts
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No-Op Insertion
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Instruction Reordering
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Stall Insertion
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Data Forwarding
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Branch Conflicts

• Solutions
• No-op insertion
• Instruction reordering
• Annulling
• Branch prediction

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Branch Conflicts (Contd)

• Annulling
• Instructions proceed through the pipeline as they
  normally would. If an instruction should not have
  been executed, because a previous instruction
  branched away from it, its results are not stored.

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Branch Conflicts (Contd)

• Branch Prediction
• Allows the compiler or pipeline hardware to make
  an assumption as to whether or not the
  conditional branch will be taken.

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RISC vs. CISC

• Each type of processor has its benefits
• Depends what type of device to be built
• If its a small device
• RISC
• If its a large device
• CISC