Sequential Logic Components

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Sequential Logic Components
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D Flip-Flops

• Combinational logic circuits are memoryless
• The outputs depends completely on the current
  inputs.
• The outputs changes as the inputs change subject
  to the gate propagation delays.
• Sequential logic circuits contain memory cells
  which record the current state of the machine.
• D flip-flops and D latches are the most commonly
  used memory cells.

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D Latches

• Basic memory cell
• A basic memory cell can be constructed by
  cross-coupling two NAND gates as follows.
• Two outputs are always complemented to each other
  when S and R are not both 0.
• If S1 and R1, Q does not change.
• If S0 and R1, Q outputs 1.
• If S1 and R0, Q outputs 0.
• The case of S0 and R0 is not allowed, because
  it make both Q and Q 1 and the future state is
  unpredictable when both S and R become 1 at the
  same time.
• Treat S and R as active-low Set (to 1) and Reset
  (to 0) signals, respectively. The cell remembers
  the value after S or R are restored to 1.

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• D Latch
• includes a RS-latch and behaves as follows
• when G0, Q does not change
• when G1, Q becomes equal to D and it changes
  as D changes
• when G changes from 1 to 0, the value of D is
  locked in the memory cell.
• D latch is level-triggered.

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D Flip-Flop

• Limitation of D-latch
• D-latch is level triggered. The output Q changes
  as D input changes when G1.
• This makes it unsuitable to be used for registers
  which require the output to be stable while the
  input is changing.
• What we need is an edge-triggered memory cell in
  which the output changes only at a point of time,
  say, the rising edge of G.
• Edge-triggered D Flip-Flop

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• Output Q (Q) does not change even D changes,
  provided that G is not at a rising edge.
• The value of D is locked into the memory cell
  at the rising edge of G and is output at Q until
  the next rising edge of G.
• D Flip-Flop is edge-triggered and suitable to be
  used to build registers whose output need to be
  stable until the next cycle.

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• Function Table of D flip-flop
• ? represents a rising edge of the signal
• Q0 represent the previous state (output) of the
  flip-flop
• two inputs
• D and G
• two complemented outputs
• Q and Q

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• Comparison of D-FF and D-latch

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• Our D-FF can be packaged to be like the D
  flip-flop in the textbook (fig1.26a)

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• D flip-flop with asynchronous active-low set and
  reset
• S0 will set Q to be 1
• R0 will set Q to be 0

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• can be packaged to be like the in the textbook
  (fig1.27)

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• D flip-flop with reset (or clear)

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• Because D flip-flop is edge-triggered, we can use
  it to build a single-bit counter as follows.
• But, we cannot do the same with level-triggered D
  latch.

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Registers

• A register is made of multiple D flip-flops.
• used to store multiple-bit data
• share the common controls of G(C), R and S.

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• Data transfer among registers
• Data can be transferred from one register at the
  same time it receives new data.