Midterm 2 Review 1

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Midterm 2 Review (1)

• Chapters 5, 6, 7, and 8 from
• Digital Design --- Principles and Practices
• by John F. Wakerly
• Topics from Midterm 1 are not explicitly asked,
  but the much of that material will be needed to
  complete answers here
• Open book, notes, calculators

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Topics to be Reviewed Today

• Latches Flip-Flops
• Registers and Counters
• State Machine Analysis

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Latches Flip-Flops

• Circuits with feedback
• Latches R-S, D
• Flip-flops D, J-K, T
• Terms set-up time, hold time, positive/negative
  edge triggered

4
Prob. 1. A NAND latch is constructed as shown
below. Each gate has a unit delay.
(a) Suppose m n y 1 for a long time.
Determine the steady-state value of z.
(z0)
(b) Given input waveforms m and n, determine the
waveforms for y and z.
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Prob. 2. The above D-Latch is constructed with
four NAND gates and an inverter. Suppose use NOR
gates for the SR latch part and AND gates
substitute the other two NAND gates. Write the
function table.
R
S
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Prob. 3. Given the following sequential logic
circuit, where the D Flip-Flops have worst-case
setup times of 10 ns, hold times of 5 ns, and
propagation delays of 15 ns. Assuming 0 ns
propagation delay through the combinational logic
block, what is the maximum allowable frequency of
the clock?
10 ns 15 ns 25 ns ? 40 MHz
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• Prob. 4. Imagine we build up a flip-flop called
  PN flip-flop with the operations clear to 0, no
  change, complement, and set to 1, when inputs P
  and N are 00, 01 , 10 , and 11, respectively.
• Derive the characteristic equation.
• Show how the PN flip-flop can be converted to a
  D flip-flop.

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Function table
Q QN QP
b. Show how the PN flip-flop can be converted to
a D flip-flop.
PD, ND
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Registers and Counters

• Registers
• storage registers
• shift registers
• Counters
• binary, decade, Gray code
• complex (skipped states)

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Prob. 5. The left figure shows a 3-bit ripple
up-count.
How about the right figure
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Prob. 6. Given a 60 MHz clock signal, design a
circuit using the counter 74x163 to generate a
clock with a cycle time of 100 ns.
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Prob. 7. Show how to configure the shift register
74x194 to realize a. Logic shift right, b. Logic
shift left, c. Arithmetic shift right, d.
Arithmetic shift left.
Note Logic shift ? fill the shifted positions
with 0s. Arithmetic shift ? propagate the
high-order sign bit to the right or shift in 0s
to the left.
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State Machine Analysis

• Moore machine configuration
• output depends only on state
• Mealy machine configuration
• output depends on state inputs
• State machine analysis

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Prob. 8. Lets consider the implementations of a
bit-serial adder. There are two inputs x1 and x0
and one output z. The inputs represent two binary
numbers, inputted bit-by-bit, with the least
significant bits presented first. The output is
their sum, as each pair of input bits is seen.
For example,
Left is the state diagram with the ½ transitions
filled.

• Is this a Mealy machine or Moore machine? (Moore)
• Fill out the above state diagram.

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Prob. 9. Analyze the clocked synchronous state
machine as shown below. Input ? X, Output ? Z.
State ? AB. Write excitation equations,
transition equations, transition/output table,
and state/output table.

J
X
A
Q
C

X
A
K
Q
R
B
FFa
Reset
Clk
J
X
BZ
Q
C
X
B
K
Q
R
A
FFb
Reset
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4. State/Output table