Combinational Design Part II with Verilog

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Combinational Design Part II(with Verilog)

• Anselmo Lastra

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Administrative
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Topics

• Positive vs. negative logic
• Design procedure
• Intro to Verilog
• Design examples
• Verification
• Simulation
• Programmable logic

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Positive and Negative Logic

• Using H to signify a logic 1 (true) is known as
  positive logic
• Misleading name -- regardless of actual voltages
  vs. gnd
• Using H to signify 0 is negative logic

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Negative Logic

• Assign 0 to H

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AND Gate Specification
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Positive vs. Negative Logic
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Bottom Line

• Not much real change
• Negative logic functions are just duals of
  positive logic ones
• OR -gt AND
• AND -gt OR

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Design Procedure

• Similar to software
• Specification likely problem description
• Formulation as truth table, Boolean function,
  or Verilog
• Optimization used to be manual, now CAD tool
• Mapping to the implementation technology
• Verification used to be manual, now simulation.
  Especially important if fab involved!

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Building Blocks and Verilog

• Well look at Verilog coding styles and syntax as
  we learn standard building blocks

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Example 1

• Output is 1 when input lt 011

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Structural Verilog

• Explicit description of gates and connections
• Textual form of schematic
• Specify netlist

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Example 1 in Structural Verilog

• module example_1(X,Y,Z,F)
• input X
• input Y
• input Z
• output F
• //wire X_n, Y_n, Z_n, f1, f2
• not
• g0(X_n, X),
• g1(Y_n, Y),
• g2(Z_n, Z)
• nand
• g3(f1, X_n, Y_n),
• g4(f2, X_n, Z_n),
• g5(F, f1, f2)
• endmodule

Can also be input X, Y, Z
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Slight Variation Gates not named

• module example_1_c(X,Y,Z,F)
• input X
• input Y
• input Z
• output F
• not(X_n, X)
• not(Y_n, Y)
• not(Z_n, Z)
• nand(f1, X_n, Y_n)
• nand(f2, X_n, Z_n)
• nand(F, f1, f2)
• endmodule

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Explanation

• Each of these gates is an instance
• In first example, they had names
• not
• g0(X_n, X),
• In second example, no name
• not(X_n, X)
• Later see why naming useful

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Gates

• Standard set of gates available
• and, or, not
• nand, nor
• xor, xnor
• buf

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Dataflow Description
module example_1_b(X,Y,Z,F) input X
input Y input Z output F assign F
(X Y) (X Z) endmodule

• Basically a logical expression
• No explicit gates

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Technology Mapping

• Full custom
• Pixel-Planes chips (machines in lobby)
• Memories, CPUs, etc
• Standard cell
• Library of cells
• Engineer determined interconnection
• Gate arrays
• Small circuits with interconnect

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Verification

• Manual
• Simulation

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Analysis of Circuit

• Next section shows disciplined way to analyze
  circuit
• To get Boolean function
• and/or Truth table
• You have enough knowledge now
• This is meant to make it more systematic

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Derivation of Boolean Func.

• Label gate outputs of input variables
• Determine Boolean functions
• Label outputs of gates fed by previously labeled
  gates
• Determine Boolean function
• Repeat 2 until done

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Lets Do This Example
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Derivation of Truth Table

• Make table with 2n rows, where n is number of
  inputs
• Label some gate outputs
• Put those labels and the final outputs on columns
  of truth table
• Work your way across

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Simulation

• The practical way to verify large circuits
• This weeks lab
• Computer figures out logic
• From schematic capture or HDL
• You specify test vectors (inputs)
• Developing these can be hard
• Simulation possibly with propagation delays

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Example 4-bit Equality

• Example 3-4 in book
• Input 2 vectors A(30) and B(30)
• Output One bit, E, which is 1 if A and B are
  bitwise equal, 0 otherwise

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Design

• Hierarchical design seems a good approach
• One module/bit
• Final module for E

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Design for MX module

• Logic function in book is
• Id call this not E, but
• Can implement as

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Design for ME module

• Final E is 1 only if all intermediate values are
  0
• So
• And a design is

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Hierarchical Verilog

• We already saw example of instantiation when we
  used AND and OR gates
• Just use module name and an identifier for the
  particular instance

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Vector of Wires (Bus)

• Denotes a set of wires
• input 10 S
• Syntax is a b where a is high-order
• So this could be 01 S
• Order will matter when we make assignments with
  values bigger than one bit
• Or when we connect sets of wires
• NOTE THIS IS NOT AN ARRAY!

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DEMO

• Lets try entering the hierarchical example
• Then simulate it

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Learned

• Simple waveform generation
• How to look at intermediate variables
• How to recompile in ModelSim
• Not to use unless you mean it
• Next slides document design
• Just for your notes

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MX

• module mx(A, B, E)
• input A, B
• output E
• assign E (A B) (A B)
• endmodule

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ME

• module me(E, Ei)
• input 30 Ei
• output E
• assign E (Ei0 Ei1 Ei2 Ei3)
• endmodule

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Top Level

• module top(A, B, E)
• input 30 A
• input 30 B
• output E
• wire 30 Ei
• mx m0(A0, B0, Ei0)
• mx m1(A1, B1, Ei1)
• mx m2(A2, B2, Ei2)
• mx m3(A3, B3, Ei3)
• me me0(E, Ei)
• endmodule

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Verilog Testbench

• Later well cover more complex Verilog
• Can use to generate test vectors
• Much more convenient than the graphical input

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Code Converters

• One code to another
• Book puts seven-segment decoder in this category
• Typically multiple outputs
• Each output has function or truth table

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Seven-Segment Decoder

• This Fridays lab Verilog of hex to LEDs
• Extended version of book example
• You may want to work out mapping (truth
  table/function) before lab

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Programmable parts

• Look at simple ones
• Switch PPT file

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Today

• Overview of CAD tools
• Design procedure
• Introduction to Verilog
• Simulation
• Simple programmable parts
• Lab preview

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Next Time

• More basic combinational circuits
• Decoder
• Encoder
• Multiplexer
• Adders
• More Verilog

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Read

• Chapter 4, Sections 1-5 and Section 8