EEL-3705%20TPS%20QUIZZES

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EEL-3705TPS QUIZZES

• Chapter 4

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Quiz 4-1
3
Using the 2x4 Decoder shown below and two-input
OR gates, design a logic circuit which implements
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Solution
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Quiz 4-2
6
Using the 3x8 Decoder shown below and two-input
OR gates, design a logic circuit which implements
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Solution
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Solution
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Quiz 4-3
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Using the 3x8 Decoder shown below and two-input
OR gates, design a logic circuit which implements
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Solution
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Quiz 4-4a
13
Using 3x8 Decoders with Active LOW Enables and
NOT gates, design a logic circuit which
implements a 4x16 decoder
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Solution
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Quiz 4-4b
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Using standard two-input and three-input logic
gates, design an encoder circuit that implements
the following truth table
a b c y1 y0
1 d 1 0 1
d 1 0 1 0
0 0 d 1 1
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Solution
1
1
1
1
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Y1
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Solution
1
1
1
1
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Y0
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Quiz 4-5
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Using standard two-input logic gates, design a
2X1 MUX which implements
Your circuit should have three inputs, Data
inputs D0 and D1, and control input S.
Hint Develop the truth table first
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Solution
D1 D0 S F
d D0 0 D0
D1 d 1 D1
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Solution
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Demonstrations
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1 bit deep 2x1 MUX

• 2 Logical Data Inputs 1 bit deep
• 1 Control Input
• 1 Logical Output 1 bit deep

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1 bit deep 4x1 MUX

• 4 Logical Data Inputs 1 bit deep
• 2 Control Inputs
• 1 Logical Output 1 bit deep

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2 bits deep 2x1 MUX

• 2 Logical Data Inputs 2 bits deep
• 1 Control Input
• 1 Logical Output 2 bits deep

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2 bits deep 4x1 MUX

• 4 Logical Data Inputs 2 bits deep
• 2 Control Inputs
• 1 Logical Output 2 bits deep

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4 bits deep 2x1 MUX

• 2 Logical Data Inputs 4 bits deep
• 1 Control Input
• 1 Logical Output 4 bits deep

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Quiz 4-6
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Using the 2X1 MUX shown below and NOT gates,
design a logic circuit which implements
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Solution
We need
We have
Let as, D0b, D1b
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Quiz 4-7
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Using standard two-input logic gates, design a
2X1 MUX with Enable which implements
Your circuit should have four inputs, Data inputs
D0 and D1, and control inputs E and S.
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Solution
D1 D0 E S F
d d 0 d 0
d D0 1 0 D0
D1 d 1 1 D1
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Solution
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Quiz 4-8
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Design a 4x1 MUX using the 2x1 MUX with enable
shown below, NOT, and OR gates
Your design should implement this equation
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Solution
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Quiz 4-9
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Using the 4x1 MUX shown below and NOT gates,
design a logic circuit which implements
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Solution
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Quiz 4-10
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Using the 4x1 MUX shown below and NOT gates,
design a logic circuit which implements
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Solution
c
c
F
c
c
a
b
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Class Design Project
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Quiz 4-11

• Module A

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Design a logic circuit (lets call this module A)
which converts a three bit signed magnitude input
into its equivalent three bit twos complement
output. Let X20 indicate a positive number and
X21 indicate a negative number.X1 and X0
represent the magnitude of the number. For
example
Module A
INPUT X2..0 OUTPUT A2..0
Hint Really this is a hint ?!!!, Develop the
truth table for all possible input combinations
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Solution
X2 X1 X0 A2 A1 A0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 0 0 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 1 0 1
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Solution
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Solution
1
1
1
1
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Quiz 4-12

• Module B

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Design a logic circuit (lets call this module B)
which computes where A is a three bit twos
complement input with a domain of -3 to 3.
How many bits are you going to need for B?
Module B
INPUT A2..0 OUTPUT B??..0
Hint This is really another hint!!!,
Precompute B in decimal for each possible A and
develop a truth table relating B to A in binary.
Assume dont care for B when A gt 3.
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Solution
A2 A1 A0 B B3 B2 B1 B0
0 0 0 -1 1 1 1 1
0 0 1 1 0 0 0 1
0 1 0 3 0 0 1 1
0 1 1 5 0 1 0 1
1 0 0 D d d d d
1 0 1 -7 1 0 0 1
1 1 0 -5 1 0 1 1
1 1 1 -3 1 1 0 1
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Solution
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Solution
1
1
1
1
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Quiz 4-13

• Module C

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Using Half Adders and NOT gates, design a logic
circuit which will compute the 2s comp of a
4-bit signed binary number
Module C
INPUT B3..0 OUTPUT C3..0
Hint
Calculate the 1s complement and add 1.
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Solution
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Quiz 4-14

• Module D

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Using Module C (i.e. 2s comp module) and the
4-bit wide 2X1 MUX shown below, design a logic
circuit which will calculate the sign magnitude
of a 4-bit 2s complement number. You may assume
maximum magnitude is 7. Your design should also
havean output labeled sign which is sign1 for
negative values.
Module D
INPUT B3..0 OUTPUT D2..0 Sign
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Solution
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Quiz 4-15

• Class Design Project

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We have the design for four modulesA 4-bit
Sign Magnitude to 2s complementB y2x-1 for
Xlt4C 4-bit 2s complement generatorD 4-bit
2s complement to Sign Magnitude
Team with two other groups. One group (X) should
implement module A One group (Y) should
implement module B One group (Z) should
implement module C,D Pick your groups and decide
who is X,Y, and Z.
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I will give a series of inputs to Group X, who
should compute A A2..0 and give it to group Y,
who then needs to compute BB3..0 and give it
to group Z who then needs to compute DD2..0
and Sign. Group D should convert the result to
decimal using a minus sign to represent a
negative number and record it on the board. Use
the index card to pass data from one module to
the next.
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Block Diagram
From Dr. Perry
Sign
X2..0
A2..0
B3..0
D2..0
A
B
C/D
Record Results On Board
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X000

• 1

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X100

• 2

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X001

• 3

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X101

• 4

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X011

• 5

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X111

• 6

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Quiz 4-16
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Let tgate15ns, calculate the worst case delay
for a 32-bit adder for the three circuits below.
Circuit Delay
Ripple Carry (2n1)tgate
Fully Parallel 2tgate
Carry Look Ahead 4tgate
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Let tgate15ns, calculate the worst case delay
for a 32-bit adder.
Circuit Delay Delay
Ripple Carry (2n1)tgate 6515ns975ns
Fully Parallel 2tgate 215ns30ns
Carry Look Ahead 4tgate 415ns60ns
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Quiz 4-17
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Given the 4-bit add/sub module shown below, let
AD, BF, ADD0, what is S in ADDER module in
hex and decimal?
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Given the 4-bit add/sub module shown below, let
AD, BF, , what is S?
DFC -3(-1)-4
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Quiz 4-18
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Given the 4-bit add/sub module shown below, let
AD, BF, ADD1, what is S in hex and decimal?
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Given the 4-bit add/sub module shown below, let
AD, BF, ADD1, what is S?
D-FE -3-(-1)-2
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Quiz 4-19
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Overflow/Underflow Detection

• Recall
• That is, if for the MSB carry_in is not equal to
  carry_out, overflow or underflow has occurred.

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Given a 4-bit adder, indicate whether each
operation below gives an overflow(O),
underflow(U), or correct (OK) answer.

• 1. D4
• 2. 6 4
• 3. 7 A
• 4. F F
• 5. 8 F

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Given a 4-bit adder, indicate whether each
operation below gives an overflow(O),
underflow(U), or correct (OK) answer.

• 1. D4 1 (OK)
• 2. 6 4 A (O)
• 3. 7 A 1 (OK)
• 4. F F E (OK)
• 5. 8 F 7 (U)

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Quiz 4-20
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Given a 4-bit adder, indicate whether each
operation below gives an overflow(O),
underflow(U), or correct (OK) answer.

• 1. D-7
• 2. 6 -4
• 3. 7 - A
• 4. F - F
• 5. 8 - 1

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Given a 4-bit adder, indicate whether each
operation below gives an overflow(O),
underflow(U), or correct (OK) answer.

• 1. D-76 (U)
• 2. 6 -4 2 (OK)
• 3. 7 - A D (O)
• 4. F - F 0 (OK)
• 5. 8 - 1 7 (U)

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Quiz 4-21
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Develop the truth table fora 2 bit signed
comparator?

• Your truth table should have four inputs
• b1 b0 a1 a0 and three outputs
• F1 (AltB)
• F2 (A gt B)
• F3 (A B)
• Assume 2-bit signed (i.e. 2s comp) values
• Hint convert to decimal and compare

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Solution
b1 b0 a1 a0 AltB AgtB AB
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 1 0 0
0 1 1 1 1 0 0
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Solution
b1 b0 a1 a0 AltB AgtB AB
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1
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Quiz 4-22
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Let AC and B7and S1..000, what is F in
hex?
F3..0
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Let AC and B7and S1..000, what is F?
F3..0
AND Operation F04
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Quiz 4-23
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Let AC and B7and S1..010, what is F in
hex?
F3..0
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Let AC and B7and S1..010, what is F?
F3..0
NOT A Operation F03
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Quiz 4-24
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Let AC and B7and S1..011, what is F hex?
F3..0
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Let AC and B7and S1..010, what is F?
F3..0
XOR Operation F0B
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Quiz 4-25
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Let A3 and B4,S1..000, What is F in hex?
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Let A3 and B4,S1..000, What is F in hex?
FAB F07
0
0
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Quiz 4-26
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Let A3 and B4,S1..010, What is F in hex?
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Let A3 and B4,S1..010, What is F in hex?
FA1 F04
0
0