The Instruction Set Architecture ISA

1
The Instruction Set Architecture ISA

• Describes the Architectural Features / Functions
  performed by the concerned CPU.
• Mainly of Interest to the System / Game
  Programmers.
• Operands happen to be Data Path Components of the
  underlying CPU Registers, Memory Locations
  and Immediate Data Integers .
• Instruction Set is composed of Assembly Language
  Instructions CPU Dependent .
• Data Defining as well as special purpose
  directives as provided by the underlying
  Assembler is also important.

2
Basic Features of Assembly Language - 1

• Assembly Instruction ( Fetched Executed by
  the CPU) CPU Dependent General Format
• ltSymbolic Labelgt optional useful for usage as
  Symbolic Operand (To be Illustrated Later)
• ltMnemonic OP Codegt ltOperand ? 1 Addressgt,
• ltOperand ? 2 Addressgt, , ltOperand ? n Addressgt
• N.B 1) Number of Operand Addresses in an
  instruction(n) may vary from 0 to 4 to be
  illustrated later .
• 2) Relative Ordering of the Operands is
  dependent on the relevant Assembler may be
  different from the CPU Designers convention.

3
Hypothetical CPU Assembly Instruction (Typical
Example )

• START MOV r1,I_a
• ltLabelgtltSeparator ( )gt ltOp CodegtltSeparator(blan
  k)gt ltSourcegtltSeparator () lt Destination gt
• CPU Reg. r1 ? Content of Memory Location I_a (M
  I_a )
• where MOV Mnemonic OP Code,
• START Instruction Label
  (Optional)
• r1 Destination Operand (Operand 1)
• ( A CPU Register GPR r1 )
• I_a Source Operand (Operand 2)
• ( A Memory Address )

4
Pentium Assembly Instruction (Typical Example )

• START MOV I_a,eax
• ltLabelgtltSeparator ( )gt ltOp CodegtltSeparator(blan
  k)gt ltSourcegtltSeparator () lt Destination gt
• CPU Reg. eax ? Content of Memory Location I_a (M
  I_a )
• where MOV Mnemonic OP Code,
• START Instruction Label
  (Optional)
• I_a Source Operand (Operand 1)
• ( A Memory Address )
• eax Destination Operand (Operand 2)
• ( A CPU Register GPR )

5
Basic Features of Assembly Language - 2

• Instruction Classes / Op-Code Classes.
• Types of Operands.
• Maximum Number of Operand Addresses in an
  instruction N
• gt The concerned machine is an N address
  Machine.
• N.B Assuming CPU Registers are much smaller in
  number than number of main memory locations hence
  no of address bits needed to access CPU registers
  is much less than the address bits needed to
  access any Main Memory location. Hence Register
  Address is treated as ½ Memory Address or 0.5
  Memory Address. Immediate values are also treated
  alike depending on its size w.r.t an Address
  Size.
• Various Operand Addressing Modes are Supported.

6
N Address Instruction Example

• a) 0 Address Instruction STC gt Set Carry
• b) 1 Operand / 1 Address Instruction JMP L1 .
  Unconditionally Jump to the Instruction Labeled
  L1
• c) 2 Operand / 0.5 0.5 Address Instruction
  
• MVI al, 80 H gt Register al (8bit) ? 80
  Hex
• c1) 2 Operand 1(0.50.5) / 2 (11) Address
  Instruction
• SWAP eax,ebx gt eax swapped with ebx .
  
• MVI B3, 0A23DEF89AH gt MB3 ?
  A23DEF89A Hex
• d) 3 Operand / 1.5 (0.5 x 3) Address
  Instruction
• ADD r1, r2, r3 gt Register r1 ? Register
  r2 Content PLUS Register r3 content
•  e) 4 Operand / 2.5 0.5 X31 Address
  Instruction
• ADD r1, r2, r3, L2gt r1 ? r2 PLUS r3,
  next instruction at Location L2 Instruction
  Pointer Not Needed

7
Various Op Code Classes /Groups

• Data Movement Group.
• Data Processing Group.
• Control Flow Group.
• Status Setting Group.
• Special Purpose (Co-Processor) Group.
• Privileged / System Group (reserved Exclusively
  for usage by the Operating System (O.S.)/
  Supervisor / Kernel ).
• N.B Assemblers normally happen to be case
  insensitive . Hence one can use both UPPER CASE
  and / or lowercase to write assembly codes.

8
Types of Operands

• 1.Registers/ CPU General Purpose Registers
• (GPRs) e.g. r2, ebx, 3 Special Purpose
  Registers
• e.g. SP, esp .
• Symbolic Convention ltReg. Idgt/ltReg.Id.gt /
  ltReg. Id.gt / ltNumericgt
• Assembler as well as area of Usage dependent
• 2.Immediate Operands (Symbolic,Numeric Generally
  Binary Integers usually expressed in Hex)
• e.g. 080 H, A, 5 .
• Symbolic Convention ltType Symbolgt ltValuegt /
  ltValue.gt ltType Symbolgt Assembler dependent
• 3. Memory Addresses e.g.I_a, 3000H , OX30000000
  refers to Main Memory / Peripheral Buffer
  locations (L. Values) can be accessed in various
  ways to be illustrated later )
• Symbolic Convention ltType Symbolgt ltValuegt /
  ltValue.gt ltType Symbolgt / lt Pre-declared (Using
  Assembler Directive) Identifiergt

9
Common Operand Addressing Modes Supported

• 1. Register Direct /Direct Register e.g.
  r1,eax
• 2. Immediate / Constant value e.g. 080 H ,
• 4 ( Decimal 4) useful for Initialization of
  any register and/or memory location.
• 3.Direct Memory e.g. I_a, 3000H, OX30000000.
  The basic way of addressing memory. Usually
  specifies logical Offset. Several other Memory
  addressing modes exist
• (to be illustrated in due course)

10
OP Codes vs. Operand Addressing Mode

• Orthogonal None of the OP Codes are related to
  any of the operand addresses e.g. Moving data
  from any source (Register /Memory/ Peripheral/
  Immediate) to any destination Register /Memory /
  Peripheral ) if controlled by a common Op Code
  say MOV then that Op Code will have identical
  machine equivalent in all these instructions.
• Non orthogonal Some OP Codes are related to
  some operand addresses (normally found )
• e.g. MVI r1, ltValue gt has a different
  machine
• Op Code than MOV r2 , ltValue gt

11
Data Movement Instructions Salient Features

• The largest class of Instructions.
• Employed to move Data from one place to another
  within the system.
• Maximum number of Operand Addresses of this Group
  2 Destination Address Source Address .
• No Flags are affected, however in some advanced
  processors conditional Movement of Data may be
  feasible e.g.
• CMOVZ eax,ebx gt CPU Reg. ebx ? Content
  of CPU Reg. eax provided Zero Flag is set.

12
Data Movement Instructions Possible Source
Destination Pairing

• Source(From) Destination (To) Common
  Op Code
• CPU Register CPU Register
  MOVE / MOV
• Immediate Data CPU Register MOVE /
  MVI Immediate
• 
  LTR (Privileged/System)
• CPU Register Memory Addr.
  STORE / MOV
• Immediate Data Memory Addr. MOV/
  STORE Immediate
• Memory Addr CPU Register
  LOAD / MOV
• Peripheral Buffer CPU Register
  MOVE/ IN
• CPU Register Peripheral Buffer
  MOVE/ OUT
• Memory Addr. Memory Addr.
  NOT ALLOWED
• CPU Register STACK
  PUSH
• STACK CPU Register
  POP

13
Data Movement Group

• General Instruction Format
• ltOp-Codegt ltSource/Destination Operand
  Addressgt ,ltDestination /Source Operand Addressgt
• The specific relative ordering of Destination
  Source varies from CPU to CPU as well as from
  Assembler to Assembler even for the same CPU.
• Assume Source as well as Operand are of the same
  size (Otherwise Assembler may not accept).
• A few common examples are given later assuming
  
• 1st Operand Address is Destination while
• 2nd Operand Address is Source. Intel Format

14
Data Movement Instruction Examples - 1

• i)  Loading any CPU Register GPR from any
  Memory location Direct Memory Addressing
• e.g. LOAD r1, I_a gtCPU Register r1 ?
  Content of the memory location I_a M(I_a)
• ii) Storing any CPU RegisterGPR in any Memory
  Location Direct Memory Addressing
• e.g. STORE I_b, r2 gt Memory Location I_b
  ?CPU Register r2s content

15
Data Movement Instruction Examples - 2

• iii)   Move from Register to Register
• e.g. MOV r1, r2 gt CPU Register r1 ?
  Content of the CPU Register r2.
• iv)  INPUT into a specific GPR from an input
  peripheral
• e.g. IN r0, KBgt CPU Register r0 ?Input
  peripheral
• keyboards Buffer
  Registers Content
• v)   OUTPUT the contents of any GPR
• e.g. OUT DISP, r0 gt Output Peripherals
  Buffer Register ? Content of CPU Register r0.
• N.BThese input/Output Instructions are normally
  found usually inside System routines / Device
  Drivers.

16
Data Movement Instruction Examples - 3

• vi) Moving Data Directly from one Memory location
  to another Memory Location ( Normally Not
  available Hence one has to do it indirectly)
• e.g. A1 B1 gtA1 ? M(B1) can be achieved by
  the following sequence of Assembly instructions
• LOAD r1, B1 gt CPU Register r1 ? M(B1)
• STORE A1,r1 gt Memory Location A1 ? r1
• vii) Assigning any GPR / Memory Location with
  Immediate Data
• e.g. MVI ri,56H gt CPU Register ri ? Hex
  Value 56
• STI A,45H gt Memory Location A ? Hex
  Value 45

17
Data Movement Instruction Examples - 4

• viii) Setting up any GPR as a pointer to a
  Memory Location Load Effective Address
• LEA r3X, A gt
• CPU Register r3 ? MS Byte of the L_Value of the
  Memory Address A A .
• CPU Register r4 ? LS Byte of the L_Value of the
  Memory Address A A .
• N.B We have used here only Direct Memory
  Addressing , other addressing modes will be
  illustrated later.

18
The STACK and its Use - 1

• A LIFO ( Last In First Out) / FILO ( First In
  Last Out ) Memory.
• Several Instances of STACK may be created
  maintained by the O.S ( One For each user process
  one for its own).
• Only one of these Stacks, however, remains
  accessible at any point of execution.
• Used in conjunction with Subroutine / User
  Routine Call , System Call , Exception Handling,
  Hardware / Device Interrupt Handling Return.
• Two types of Stack are in use common System
  Stack User Stacks ( Separate for each user
  process).
• All stacks are accessed via explicit registers (
  The Stack Pointer) Base Pointer (wherever
  present).

19
The STACK Content A Stack Frame

• A) The Activation Record
• a) Parameters.
• b) The Previous Execution Status
  ( The PSW).
• c) Return Instruction Pointer.
• d) Return Stack Frame Pointer
• e) Local Variables.
• B) All the CPU Registers being used
• ( CALLER Saved / CALLE saved) .
• A) B) together represents the Thread of
  Execution ( Will be Highlighted in the O.S.
  Class).

20
Stack Manipulation Instructions - 1

• Some commonly used instructions are illustrated
• 1) Initializing Stack Pointer Register
• LXI SP, 0AAAFH gt Initialize Stack Pointer
  to Address AAAFH i.e. the Current Stack Top is at
  AAAFH and the Stack is empty.
• N.B Stack is made to grow from the address AAAF
  towards lower address , in order to avoid
  clashing with other allocations that starts from
  lower to higher address.

21
Stack Manipulation Instructions - 2

• 2) Pushing Data Values in Stack General steps
  adopted are as follows
• A1 DW 023ABH A1 is a 16 Bit Location
  Initialized to 23AB Hex Lower Address ?
  LSByte(Little Endian Convention)
• LXI SP, 0AAAFH Initialize Stack Pointer
  to AAAF Hex
• LOAD r0X, A1 Register Pair r0 r1 ?
  Content of the Memory Location A1M(A1) with
  r0 containing MSByte r1 contains LSByte
• PUSH r0X SP ? SP-1 i.e. Stack grows
  from Higher to Lower Address M(SP) ? (r0) i.e.
  Content of r0 MSByte stored in the Memory
  Location pointed to by the Stack Pointer SP
  (Address AAAE H) Higher Address ? MSByte
• SP ? SP-1 SP now points to Location AAAD
  Hex
• M(SP) ? (r1) i.e. Content of r1 LSByte
  stored in the Memory Location AAAD Hex.

22
Stack Manipulation Instructions - 3

• N.B The Instruction Pointer Register Content
  (Return Address) is pushed automatically by the
  CPU Control Unit onto Stack while executing
  CALL / System Call (Software Interrupt)
  Instructions (to be illustrated later) but
  everything else, if needed to be preserved in
  stack, are to be done by the programmer using
  explicit instruction (s) (usually PUSH).

23
Stack Manipulation Instructions - 4

• 2) Popping Data Values from Stack General
  steps adopted are as follows
• It is assumed that the Stack Pointer Register
  (SP) is already pointing to the Current Stack Top
  Location (which is Filled).
• POP r0X CPU Register r0 ? Content
  of the Memory Location Pointed to by the Stack
  Pointer M(SP) SP ? SP1
• CPU Register r1 ?
  Content of the Memory Location Pointed to by the
  Stack Pointer M(SP) SP ? SP1
• Note Stack shrinking from Lower towards Higher
  Address.
• N.B The Return Addresses are retrieved from
  stack into the Instruction Pointer automatically
  by the Control Unit of the CPU while executing
  RET instruction (to be illustrated later) but
  everything else is to be retrieved from stack by
  the programmer employing explicit (usually POP)
  instruction.

24
Passing Parameters via Stack

• Principle
• Save the special Base Pointer Register here r2X
  in Stack.
• Create space in stack by suitably adjusting Stack
  Pointer creating a Stack frame ..
• Put parameters in the created stack frame using
  Base Pointer Register (r2X) as parameter index.
• On entering the called routine retrieve the
  parameters from stack employing Base pointer
  register(r2X).
• Illustrative Example Will be given later.

25
Data Processing Instructions

• These are used to accomplish the various
  arithmetic and
• logical operations, involving either CPU
  Registers (GPRs),
• Memory locations and/or Immediate Data.
• General Format
• ltOP Codegt ltOperand 1 Addressgt , ltOperand 2
  Addressgt
• ,ltOperand 3 Addressgt
• Meaning
• Destination Operand Address ? (Source 1 Operand
  Address Content)
• 
  ltOperator as specified in the Op Codegt
• 
  (Source 2 Operand Address Content)

26
Data Processing Instructions Features 1

• 1. Unless otherwise specified most operations
  happen to be Binary in nature some unary
  operations like NOT can be there.
• 2. In some CPUs all 3 Operand Addresses are
  specified explicitly while in some only 1 or 2
  Operand Addresses are specified.
• 3. The relative ordering of the Destination
  Operand Address as well as the Source Operands
  varies from CPU to CPU as well as from assembler
  to assembler even for the same CPU.

27
Data Processing Instructions Features 2

• 4. In case of 2 Operand instruction (as in our
  sample machine) one of the two Source Operands
  also acts as the Destination i.e. the Original
  content of this Operand Address is destroyed post
  instruction.
• 5. In case of single operand instruction the
  other source operand which also acts as the
  destination is a special CPU register termed as
  the Accumulator (ACC).
• 6. Each of these instructions employs ALU
  (Arithmetic Logic Unit).
• 7. Each of these instructions normally affect ALL
  the CPU condition code Flags except those
  mentioned explicitly.

28
Data Processing Instructions Examples - 1

• Assumptions
• a) 2 Operand Address Instruction where 1st
  Operand happens to be One of the Sources as well
  as Destination for Result.
• b) Both Operands happen to be CPU
  Registers/Register Pair GPRs. However in some
  Modern Day machines one or both operands can also
  be memory locations.
• c) In some cases , as will be illustrated in due
  course, 3 Operand addresses may be used.

29
Data Processing Instructions ( The Arithmetic
Group) - 1

• ADD r1, r2 gt CPU Register r1 ? (r1) PLUS
  (r2)
• ADC r1,r2 gt r1 lt- (r1) PLUS (r2) PLUS Cy
  Flag
• SUB r3,r4 gt r3 lt- (r3) MINUS (r4) .
• SBB r3,r4 gt r4 lt- (r3) MINUS (r4) PLUS Cy
  Flag
• ADI r3, 078H gt r3 lt- (r3) PLUS 78 Hex Add
  Immediate
• SUI r1, 056H gt CPU Register r1 ? (r1) MINUS
  56 Hex.
• INR r1 gt Increment the content of CPU Register
  r1 . Affect ALL flags except Carry Overflow.
• DCR r2 gt Decrement the content of CPU Register
  r2 . Affect ALL flags except Carry Overflow.
• COMP r1, r2 gt Compare (r1) with (r2) I.e.
  perform the operation (r1) MINUS (r2) but do
  not store the Result and set Status Flags
  accordingly i.e. Set ZERO if (r1) (r2) , Set
  Borrow if (r1) lt (r2), Do not Set borrow if
  (r1) gt (r2)
• N.B No distinction between signed Unsigned
  Operands here.

30
Data Processing Instructions ( The Arithmetic
Group) - 2

• 10. MUL r3 gt Multiply Unsigned I.e. perform
  unsigned Multiplication (r0) X (r3) where
  CPU Register Pair r0X stores the result with
  r0 containing the MS Byte and r1 containing
  LSByte of result. Here one source as well as
  the Destination are implied (ACCUMULATOR Based)
• 11. DIV r3 gt Perform Unsigned Division
  (r0)(r1) / (r3) with unsigned quotient in r1
  and unsigned remainder in r0. Here one source
  as well as the Destination are implied
  (ACCUMULATOR Based) .
• N.B Shifting Logically Left by n bits gt
  Multiply by 2 n .
• Shifting Logically Right by n bits gt
  Divide by 2 n .
• 12. IDIV r3 gt Signed Division (employs
  different Methodology).

31
Single OP Code with various Operands

• 13. Signed Multiplication (Employs diff Algorithm
  / Booths)
• a) IMUL r2 gt Perform signed Multiplication
  (r1) X (r2) where CPU Register Pair r0X
  stores the result with r0 containing the MS Byte
  and r1 containing LSByte of result. Here one
  source as well as the Destination are implied
  (ACCUMULATOR Based)
• b) IMUL r1,r2 gt Perform signed
  Multiplication (r1) X (r2) where CPU
  Register r1 stores the truncated result (
  LSByte) only. Here one source acts as well as
  the Destination .
• c) IMUL r1,r2,15H gt Perform signed
  Multiplication (r2) X 15 Hex) and store the
  LSByte of the result in CPU register r1. Here
  both the sources as well as the Destination are
  explicitly specified.
• .

32
Data Processing Instructions ( Conversion
Group)

• 1. Special adjustment Instructions used to adjust
  the result in BCD like DAA (Decimal Adjust after
  Addition) in Intel Family.
• 2. Special Operand adjustment Instructions prior
  to certain Operations to ensure that generated
  result conforms to the specified format(s) like
  AAD ( ASCII Adjust before Division) in Intel
  Family.

33
Data Processing Instructions ( The Logical
Group) - 1

• 1. AND r1,r2 gt CPU Register r1 ? (r1)
  Logical Bit Wise ANDing with (r2) Logical
  Multiplication.
• 2. TEST r1,r2 gt Perform (r1) Logical Bit Wise
  ANDing with (r2) I.e. (r1) . (r2) and set
  Flags accordingly but DO NOT STORE the Result..
• 3. OR r1,r2 gt CPU Register r1 ? (r1)
  (r2) Logical Addition / Bit wise Oring of (r1)
  with (r2).
• 4. NOT r0 gt r0 ? 1s Complement of (r0)
• 5. NEG r1 gt r1 ? 2s Complement of (r1).

34
Bit Manipulation Instructions - 1

• Some high level processors like Pentium provides
  individual bit test Set Instructions like
• a) BT r0X,11 gt Tests 11th bit from
  left ( b0 of r1 as the 1st bit of register pair
  r0r1) i.e. b2 bit of the register r0 and
  sets Carry Flag accordingly
• ( Cy lt-1 if that bit is set, Cylt- 0
  if that bit is NOT set).
• b) BTS r1, 7 gt Sets 7th bit (b6 bit)
  of CPU Reg. r1 to 1.
• c) BTR r2X, 9 gt Clears 9th bit of CPU
  Reg. Pair r2r3 i.e. clear b0 bit of the
  register r2
• d) BTC r3,5 gt Invert 5th bit (b4 bit
  ) of CPU Reg. r3.

35
Bit Manipulation Instructions 2( Shift
Rotate Group)

• Shifting a Register Pair / Register Content by
  specified amounts to the Left or Right with
  vacant positions filled up by Zeros Logical
  Shift .
• Shifting a Register Pair / Register Content by
  specified amounts to the Right with vacant
  positions at the right filled up by the sign bit
  Arithmetic Shift .
• Rotating Register Pair / Register Content by
  specified amounts to the Right /Left through
  the carry (Cy) Flag.

36
The LEFT SHIFT Operation
LSHIFT ri,1 gt Open ( Logically) left shift
(ri) by 1 bit.
b(iPresent ? b(i-1) Prev. for i 1..(n-1)
n7/15/31 CARRY/BORROW Flag Present?
b(n-1)Prev. i..e. Prev. CARRY/BORROW is


OVERWRITTEN. b0Present? 0
Affects ZERO SIGN Flags too, Does not affect
OVERFLOW Flag
b(n-1) b(n-2) b(i) b(i-1)
b(0)
b(n-1) b(n-2) b(i1) bc(i) b(i-1)
b(1) b(0)
CY Flag
0
37
The RIGHT SHIFT Operation
RSHIFT L ri,1 gtOpen / Logically Right Shift
(ri) by 1 bit
b(i)Present ? b(i1) Prev. for i
0..(n-2) n7/15/31 CARRY/BORROW Flag
Present? b(0)Prev. i..e. Prev. CARRY/BORROW

is
OVERWRITTEN b(n-1)Present? 0
Affects ZERO SIGN Flags too, Does not affect
OVERFLOW Flag
b(n-1) b(i1) b(i)
b(2) b(1) b(0)
b(n-1) b(n-2) b(i) b(i-1)
b(1) b(0)
CY Flag
0
38
The Arithmetic Right SHIFT Operation
ARSHIFT ri,1 gt Right Shifted ri
Arithmetic Where biPresent ? b(i1)Prev.
for i 0..(n-2) n7/15/31
CARRY/BORROW Flag Present? b0Prev. i.e.
Prev. CARRY/BORROW
is
OVERWRITTEN. b(n-1)Present?
b(n-1)Prev. . Sign is Preserved in its
designated Position. Affects ZERO Flag
too, does not affect OVERFLOW SIGN Flags.
b(n-1) b(i1) b(i)
b(2) b(1) b(0)
b(n-1) b(n-2) b(i) b(i-1)
b(1) b(0)
CY Flag
39
The ROTATE LEFT Operation
RAL ri,1 gt CLOSE Left Shifted ri through
Carry once where CARRY/BORROW Flag Present ?
b(n-1) Prev. b(i) Present ? b(i-1)
Prev. for i 1..(n-1) n7/ 15/31 b0
Present ? CARRY/BORROW Flag Prev.Cy_In i.e.
CARRY/BORROW is Preserved in the LSBit.
Affects CARRY/BORROW, ZERO SIGN Flags only,
does not affect OVERFLOW Flag.
b(n-1) b(n-2) b(i) b(i-1)
b(1) b(0)
b(n-1) b(i1) b(i)
b(2) b(1) b(0)
CY Flag
40
The ROTATE RIGHT Operation
ROTATE RIGHT ri CLOSE Right Shifted ri thro.
Carry Where CARRY/BORROW Flag Present? b0
Prev. c(i)Present ? b(i1) Prev.
for i 0..(n-2) n7/15/31 c(n-1)
Present ? CARRY/BORROW Flag Prev.Cy_In.
i.e . CARRY/BORROW is Preserved in the MSBit.
Affects CARRY/BORROW, ZERO SIGN Flags
only, does not affect OVERFLOW Flag.
b(n-1) b(i1) b(i)
b(2) b(1) b(0)
b(n-1) b(n-2) b(i) b(i-1)
b(1) b(0)
CY Flag
41
Bit Manipulation Instructions ( Multi Bit Shift
Rotate )

• Shifting a Register Pair / Register Content by
  specified amounts to the Left or Right with
  vacant positions filled up by Zeros Logical
  Shift .
• e.g. SHL r0X, 2 ? r0r1 ? (r0)(r1) Left
  Shifted by 2 bits with the following outcome .
• (r0) Current b7b6 goes out . CY ? b6, bi
  ? Previous b(i-2)
• 
  for i 2..7
• b1 ? Previous b7 of r1 , b0 ?
  Previous b6 of r1
• (r1) Current b7b6 goes out to r0 and bi
  ? Previous b(i-2)
• 
  for i 2..7 b1 ? 0 , b0 ? 0.
• Ex a) SHR r2X , 4 (Shift Right Arith. Reg.
  Pair r2r3 by 4 bits)
• b)RAR r4X , 5 (Rotate Right Reg. Pair
  r4r5 by 5 bits)
• c) RAL r6 , 3 (Rotate Left Reg. Pair
  r6r7 by 3 bits)

42
Control Flow Instructions

• Helps to alter the normal sequential flow of
  control. General Format
• ltOp-Codegt ltSymbolic Target Address gt /
• ltTarget Address
  Computation Constantgt
• Among the several types the following stands
  out
• a) JUMPing / Branching (Conditionally /
  Unconditionally).
• b) LOOPing Conditionally / Unconditionally.
  
• b) CALL ( Conditionally / Unconditionally).
• c) RETurn (Conditionally / Unconditionally).
• d) System Call / SOFTWARE INTERRUPT ( INT n
  )
• e) IRETurn ( Return from Interrupt /
  Exception Handler)
• In addition , the following activities will also
  halt the normal flow of execution and causes a
  branching to some other place.
• 1) Signal from a Device ( Device/ Hardware
  Interrupt).
• 2) Exception ( Internally generated
  unintentionally while executing some program).

43
Control Flow Instructions - (Salient Features) -
1

• Most of these Instructions depends on the
  Condition Code FLAG(s) setting.
• Normally barring a few special class of
  Instructions in some particular processor, none
  of the Instructions under this Group/Class sets
  /affects any of the Flags.
• Most Control Flow Instructions possesses a Single
  Operand i.e. the Target Address except for some
  complex instructions like Compare Branch .
• All types of Interrupts (Software, Hardware,
  Exception) causes the CPU to switch Execution
  Mode (User to Kernel).
• In some cases the Control Flow is directly
  affected by the underlying Control Unit
  (especially while Handling Exceptions).

44
Control Flow Instructions - (Salient Features) -
2

• 6. The Target Address Location must always
  contain
• some Machine Op-Code i.e the associated
  Assembler
• should have the feature to prevent any
  illegal jumping
• in the data area.
• e.g. consider the following code segment
• ORG 4000H Set Up
  Location Counter at 4000H
• A1 DW 2263H A1 being
  a 16 Bit Variable having a
• 
  Location 4000H initialized to 2263 H
• .
• JMP A1 This
  MUST NOT BE ALLOWED by
• 
  the Underlying Assembler

45
Control Flow Instruction (Example) 1

• JZ Next gt Jump to the instruction having the
  label NEXT if previous result Zero (0) I.e.
  ZERO Flag is Set.
• JNC ELSE gt Jump to the instruction labeled ELSE
  if
• previous result has not Set the Carry.
• JMP L1 gtJump unconditionally to the instruction
  labeled L1.

Branching (Conditional / Unconditional)
46
Control Flow Instruction (Example) 2

• Compare Branch Instruction
• BEQ r1,r2, L1 gt Jump to the Instruction
  Labeled L1 if contents of the CPU Registers
  r1 happens to be equal to the contents of
  the CPU Register r2
• i.e. Go to L1 iff (r1) (r2)

47
Control Flow Instruction (Example) 3

• Loop Instruction
• LOOP L1 It acts in the following manner
• 1. Decrement CX (here r4X pair)
• 2. Jump to the Instruction Labeled L1 if
  contents of the CPU Registers r4r5 ! 0
• otherwise go to execute next Instruction.

48
Control Flow Instruction (Example) 3

• 3) CALL / RETURN (Unconditionally/Conditionally
  ) / IRET
• This allows calling returning from
  subroutines Interrupt / Exception Handlers
  analogous to HLL.
• (1) CALL MUL gt Call Routine named MUL
  Unconditionally (After preserving return address
  in Stack)
• (2) CZ PROCESS gt Call Routine Process if
  previous Result Equals Zero (After preserving
  return address in Stack)
• (3) RETgt Return from the current routine
  Unconditionally to the return address preserved
  in Stack Top which is popped out
• (4) RETC gt Return from current routine if
  Carry Flag is Set to the return address
  preserved in Stack Top which gets popped.
• (5) IRETgt Return from the current Interrupt
  Handler Unconditionally to the return address
  preserved in Stack Top which is popped out. The
  preserved Flags are also popped out.

49
Special Control Flow Instruction

• 4) Software Interrupt / Supervisor (O.S.) Call .
• e.g. RST n / INT n ( n usually
  unsigned Integer 0.. 100) say RST 1 / INT 1
• gt Go to the Address location 18 i.e. Hex
  Address 0008 (in our machine) after preserving
  return address Current Computation Status in
  System stack and execute the instruction stored
  in 0008. Here 1 acts as the Interrupt Vector.
  This will cause the program to invoke some O.S.
  service routine whose entry point is stored in
  the vectored address (here 0008H).

50
Software Interrupt Instruction (Distinctive
Features)

• The Current Computation Status are available in
  Condition Code Flags as well as in some System
  Flags all of which can be accessible through a
  Special Register termed as Program Status Word
  (PSW).
• The System Stack is a special stack reserved for
  use by the Operating System (O.S.) / Supervisor
  alone. It is used by the O.S. to keep track of
  all the different processes (to be illustrated
  later) running in the system.

51
Software Interrupt Instructions (Salient
Features) - 1
1. Software Interrupt Instructions are normally
Unconditional i.e. they do not depend on
the STATUS Flags to affect the transfer. 2.
Software interrupt Instructions helps the CPU to
jump to a location (after preserving the
return Address Current STATUS Flags in
System Stack ) which contains another jump
instruction to the relevant Interrupt
Service Routine(s) ISRs . These ISRs are
NOT part of the original program and mostly
brought into main memory on DEMAND. Hence
this truly represents RUN TIME BINDING of
Code.

52
Software Interrupt Instructions (Salient
Features) - 2

3. Typical invocation sequence of Software
Interrupt instruction e.g. a) Specific CPU
Register ? ISR Selection Code Helps the
CPU to Specifically Choose the required Service
b) Software Interrupt Instruction -gt
To invoke the Service. 4. The Interrupt Service
Routines/ ISRs mostly are employed to
achieve the following Start / Invoke
the selected Peripheral Interface Driver Program
by initializing the relevant
Peripheral Interface Command
Register(s) using some Privileged Instruction.
.
53
Software Interrupt Instructions (Salient
Features) - 3

• 5. Software Interrupt Instructions are NOT used
  to handle device interrupts OR exceptions arising
  out of any erroneous operations . These are
  handled by the Operating System triggered by
  some device Hardware (to be discussed later) or
  by some operation performed by the currently
  executing program Division by Zero , Page
  Fault etc.
• 6. System Stack is normally accessible under
  Kernel Mode.

54
Software Interrupt Instructions (Difference from
CALL)

• CALL Instruction does not preserve the System
  Status in Stack (User Stack here) .
• The actual Target Routine address is specified in
  the CALL instruction itself ensuring a single
  level jump while INTERRUPT always makes a 2 Level
  Jump first to the Computed Interrupt Vector then
  jumps to the specified Interrupt Service Routine
  (ISR) as specified in that Interrupt Vector.
• There exists some scope of making the Target
  Code (called routine) part of the Program itself
  during Linking/Loading phase. (Static / Link or
  Load Time Binding) .
• CALL does not change the Mode of Execution.
• CALL requires RET while Interrupt requires IRET
  to exit.

55
Role of Software Interrupt Instruction in the
Usage of Peripherals

• User program asks for Device Service by employing
  specific Software Interrupt / O.S. Call / Sys
  Call Instruction.
• This will cause the currently running user
  program to switch to Kernel / Supervisor Mode
  from its present user mode.
• Inside Kernel Mode , the CPU sends the Command to
  the Peripheral Command Register (s) , it also
  sets up the Peripheral Interface Buffer.
• The Peripheral Interface starts the relevant
  device the concerned user program goes to
  WAIT/BLOCKED state CPU takes up another user
  program for execution.
• On completion / Error, the peripheral interface,
  sends another interrupt (A Hardware / Device
  Interrupt ) to the CPU.
• In response, the CPU , with the help of O.S. will
  either reload the Interface Buffer restarts the
  operation OR alternately generates a proper
  Message.
• Subsequently the BLOCKED /WAITING user Program
  is made Ready to restart (if needed) under User
  Mode.

56
Status Setting Instructions (Salient Features)

• Ø Operand instructions ( Used to Selectively Set
  STATUS of
• Some Designated
  Flags/ Designated Bits)
• e.g. STC ? Set Carry
• CLC ? Clear Carry
• .
• N.B One can affect ALL the flags together
  indirectly by employing some special Data
  Processing Instruction
• e.g. OR ri,ri ? ri ? (ri) BITWISE OR (ri)
  normally clears ALL Flags
• NOP (No Operation) ? Dummy Instruction used to
  consume CPU Time without affecting anything
  i.e.Helps to preserve Current Status

57
Special Co-Processor Group Instructions
(Salient Features)
These are present in most Modern Day CPUs but are
employed to program separate Execution Units
which are fabricated along with the CPU on the
same die. Some typical examples (involving
Pentium) are  given below     1)
Floating Point Unit ( FPU) instructions. e.g.
FLD lt64 bit Data Locationgt ? Push 64bit Real
Data into FPU Register Stack        2) Multi
Media (MMX) instructions. e.g. PACKSSDW
ltMemory1gt,ltMemory2gt ? Pack and saturate pack 4
signed 32bit words from Memory1 and 4 signed 32
bit words from Memory 2 into Memory 1 New
Classes are being introduced regularly.

58
Privileged Instructions (Salient Features)

• These are Instructions normally available to
  the Operating System I.e. used by the O.S.
  writers.
• Mostly these are used to manage / check status
  of all System Resources (CPU Time, Memory System,
  Device
• Interfaces) Normally done under KERNEL
  Mode.
• Typical Example (in Pentium)
• 1) LMSW lt16 bit Register/ 16 bit Memory
  valuegt
• Load Machine Status Word , bits 0 to 15 of the
  register CR0 from the specified Operand.
• 2) LAR lt16 bit Registergt,ltSegment
  Descriptorgt
• Loads ACCESS RIGHTS from the Segment Descriptor
  to the designated Register.