Project 4 Pipelined MIPS

1
Project 4 - Pipelined MIPS
MEM
_PCSrc
WB_RegWrite
1
MEM
_
btgt
MEM
_
btgt
reset
IF_pc_next
reset
0
W
Control
ID
_op
W
reset
M
reset
IF_pc4
M
W
E
IF_pc
EX
_
btgt
ID
_pc4
EX
_pc4
EX
_extend
EX
_
offset
4
reset
MEM
_
Branch
WB_
RegWrite
ltlt2
PC
EX
_
Zero
RegWRite
ID
_
rs
MEM
_
Zero
EX
_rd1
RN1
RD
ADDR
RD1
5
32
Zero
ID
_
rt
Instruction
MemWrite
RN2
EX
_ALUSrc
5
Register
ALU
Memory
ADDR
WB_wn
WN
File
Data
5
RD2
WD
RD
Memory
WB_memout
WB
_wd
WD
MemRead
16
32
EX
_funct
ALU
MEM
_
memout
Control
6
ID
_immed
ID
_extend
WB
_
ALUOut
EX
_RegDst
MEM
_
MemRead
ID
_rt
EX
_rt
EX
_ALUOp
5
ID
_rd
EX
_RegRd
MEM
_RegRd
WB
_RegRd
5
EX
_rd
IF/ID
ID/EX
EX/MEM
MEM/WB
2
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3
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4
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5
(No Transcript)