LECTURE MOS CAPACITANCES

1
LECTURE MOS CAPACITANCES
EEE C443 Analog and Digital VLSI Design
2

• Chemical vapor deposition (CVD) a deposition
  process in which a non-volatile film forms on the
  substrate due to the reaction of vapor phase
  precursors.
• Physical vapor deposition (PVD) a deposition
  process in which the solid or liquid source
  material is converted to a vapor by mechanical or
  thermal means, transported to the substrate, and
  condensed from the vapor onto the substrate.
  Sputtering, which mechanically knocks the source
  atoms loose, is the most common PVD method in
  semiconductor manufacturing, and the two terms
  are often used interchangeably.

3
MOS CAPACITANCESSCALING TECHNIQUES

• SHORT CHANNEL EFFECTS

4
Dynamic Behavior of MOS Transistor
5
(No Transcript)
6
The Gate Capacitance
7

• Voltage dependent capacitances--- dynamic gate
  capacitance, junction capacitances.
• Voltage independent capacitances. overlap
  capacitances CGDOV CGSOV

8
(No Transcript)
9
(No Transcript)
10
MOSFET CAPACITANCES
11
(No Transcript)
12
(No Transcript)
13
(No Transcript)
14
Average Gate Capacitance
Different distributions of gate capacitance for
varying
operating conditions
Most important regions in digital design
saturation and cut-off
15
JUNCTION Capacitances -gt Cdb, Csb
16
Junction Capacitance
17
(No Transcript)
18
(No Transcript)
19
(No Transcript)
20
(No Transcript)
21
(No Transcript)
22
Linearizing the Junction Capacitance
Replace non-linear capacitance by large-signal
equivalent linear capacitance which displaces
equal charge over voltage swing of interest
23
EQUIVALENT LARGE SIGNAL AREA CAPACTIANCE
24
(No Transcript)
25
Junction Capacitance
26
(No Transcript)
27
(No Transcript)
28
Scaling Techniques
29
ROADMAP FOR ULSI TECHNOLOGY
Technology Generation 250 nm 180 nm 150 nm 130
nm 100 nm 70 nm 50 nm Year (Production) 1997 199
9 2001 2003 2006 2009 2012 DRAM/SRAM 256/64M 1G/2
56M 1G/256M 4G/1G 16G/4G 64G/16G 256/64G DRAM
chip (cm2) 2.8 4.0 4.45 5.6 7.9 11.2 15.8 DRAM
cost (??bit) 120 60 30 15 5.3 1.9 0.66 Wafer
Diameter (mm) 200 300 300 300 300 450 450 Logic
gates/cm2 3.7-8M 6.2-14M 10-16M 18-24M 39-40M 84
-64M 180-100M Logic chip (cm2) 3-4.8 3.4-8 3.85-8
.5 4.3-9 5.2-10 6.2-11 7.5-13 Frequency
(GH) 0.3-0.75 0.5-1.2 0.6-1.4 0.7-1.6 0.9-2.0 1.2
-2.5 1.5-3.0 ? cost (m ?T) 3000 1735 1000 580 255
110 49 ASIC NRE cost (m ?T) 50 25 20 15 10 5 2.5
Power/chip (W) 70 90 110 130 160 170 175 Power
Supply 2.5-1.8V 1.8-1.5V 1.5-1.2V 1.5-1.2
V 1.2-0.9V 0.9-0.6V 0.6-0.5 Levels of
Metal 6 6-7 7 7 7-8 8-9 9 Oxide Thickness
(nm) 4-5 3-4 2-3 2-3 1.5-2 lt1.5 lt1 Xj at Channel
(nm) 50-100 36-72 30-60 26-52 20-40 15-30 10-20 X
j Contact (nm) 100-200 70-140 60-120 50-100 40-80
15-30 10-20 Nominal Leff (?m) 140-210 100-151 8
4-126 73-109 56-84 44-54 28-42 Leff Variation
lt20 lt20 lt20 lt20 lt20 lt20 lt20 Id sat (?/
?m ) 600/280 600/280 600/280 600/280 600/280 6
00/280 600/280 Ioff (nA/ ?m ) 1 1 3 3 3 10 10 N
umber of I/O pins 1450 2000 2400 3000 4000 5400 7
3002

Taken as 70 of the technology parameter
NMOS/PMOS
30
Adv. of Scaling

• Improvements
• Density
• Speed
• power

31
SCALING THEORY
RESULTS Density/Chip D Delay/Ckt t Power
/Circuit P
32
Why Scaling?

• Technology shrinks by 0.7/generation
• With every generation can integrate 2x more
  functions per chip chip cost does not increase
  significantly
• Cost of a function decreases by 2x
• But
• How to design chips with more and more functions?
• Design engineering population does not double
  every two years
• Hence, a need for more efficient design methods
• Exploit different levels of abstraction

EEE C443 Analog and Digital VLSI Design
33
Technology scaling

• Currently, technology scaling has a threefold
  objective
• Reduce the gate delay by 30 (43 increase in
  frequency)
• Double the transistor density
• Saving 50 of power (at 43 increase in
  frequency)
• How is scaling achieved?
• All the device dimensions (lateral and vertical)
  are reduced by 1/s
• Concentration densities are increased by s
• Device voltages reduced by 1/s (not in all
  scaling methods)
• Typically 1/s 0.7 (30 reduction in the
  dimensions)

34
Scaling Models
EEE C443 Analog and Digital VLSI Design
35
Non scaling functions

• Material related parameters do not change with
  scaling like
• Energy bandgap
• Work function

36
FULL SCALING-

• Provides basic guideline to design of scaled
  MOSFETs

37
FULL SCALING---in accordance with poison
equationesi (d2V(x) /dx2)    ?(x)   q (ND
- NA- - n p)

• The scaling variables are
• Supply voltage Vdd ? Vdd / s
• Gate length L ? L / s
• Gate width W ? W / s
• Gate-oxide thickness tox ? tox / s
• Junction depth Xj ? Xj / s
• Substrate doping NA ? NA ? s
• This is called constant field scaling because the
  electric field across the gate-oxide does not
  change when the technology is scaled

38
Some consequences of full scaling esi (d2V(x)
/dx2)    ?(x)   q ND

• 30 scaling in the constant field regime (s
  1.43, 1/s 0.7)
• Device/die area W ? L ? (1/s)2 0.49
• In practice, microprocessor die size grows about
  25 per technology generation! This is a result
  of added functionality.
• Transistor density (unit area) /(W ? L) ? s2
  2.04
• In practice, memory density has been scaling as
  expected. (not true for microprocessors)

39
Some consequences of full scaling

• Gate capacitance W ? L / tox ? 1/s 0.7
• Drain current (W/L) ? (V2/tox) ? 1/s 0.7
• Gate delay (C ? V) / I ? 1/s
  0.7 Frequency ? s 1.43
• In practice, microprocessor frequency has doubled
  every technology generation (2 to 3 years)! This
  faster increase rate is due to two factors
• the number of gate delays in a clock cycle
  decreases with time (the designs become highly
  pipelined)
• advanced circuit techniques reduce the average
  gate delay beyond 30 per generation.

40
Some consequences of full scaling

• Power dissipation C ? V2 ? f ? (1/s)2 0.49
• Power density active power per chip area
• (1/tox ? V2 ? f ) / area ? 1
• Active capacitance/unit-areaPower dissipation is
  a function of the operation frequency, the power
  supply voltage and of the circuit size (number of
  devices).If we normalize the power density to V2
  ? f we obtain the active capacitance per unit
  area for a given circuit. This parameter can be
  compared with the oxide capacitance per unit
  area 1/tox ? s 1.43
• In practice, for microprocessors, the active
  capacitance/unit-area only increases between 30
  and 35. Thus, the two fold improvement in logic
  density between technologies is not achieved.

41
Electromigration (1)
42
Limitations of full scaling

• Requirement of reducing the voltage by the same
  factor is too restrictive because there is a
  general reluctance to depart from standardized
  voltage levels of previous generation
• Reason---Entire set of analog drivers of
  peripheral circuitry (communicating with digital
  design) need to be redesigned
• Or we will require multiple power supplies and
  complicated level shifters

43

• So power supply voltage is seldom scaled in
  proportion to channel length.
• As a result---electric field has been gradually
  rising over the generations rather than staying
  constant
• Result---electro-migration, hot carrier injection
  in gate oxide
• And High power dissipation

44
C V scaling

• As the field across oxide is increasing, it is
  necessary to develop a set of guidelines that
  allow electric field to increase.
• It is desired that both vertical and lateral
  electric field change by same multiplication
  factor.so that shape of electric field pattern is
  preserved.
• This assures the short channel effects do not
  become worse upon scaling.
• But , higher fields cause reliability problem

45
Constant voltage scaling
If the power supply voltage is maintained
constant the scaling is called constant voltage.
In this case, the electric field across the
gate-oxide increases as the technology is scaled
down. Due to gate-oxide breakdown, below 0.8µm
only constant field scaling is preferred.
46

• The scaling variables are
• Supply voltage Vdd ? Vdd
• Gate length L ? L / s
• Gate width W ? W / s
• Gate-oxide thickness tox ? tox / s
• Junction depth Xj ? Xj / s
• Substrate doping NA ? NA ? s2

47
Some consequences of CV scaling esi (d2V(x)
dx2)    ?(x)   q ND

• Device/die area W ? L ? (1/s)2 0.49
• Transistor density (unit area) /(W ? L) ? s2
  2.04
• Carrier velocity

48
Some consequences of CV scaling

• Gate capacitanceCGS W ? L / tox ? 1/s 0.7
• Drain current (W/L) ? (V2/tox) ? s 1.43
• Gate delay (CGS ? VDS) / ID ? 1/ s 2 0.49
• Frequency ? s2 2.04

49
Some consequences of CV scaling

• Power dissipationVdsIds CGS ? V2 ? f
  ? s 1.43
• Power density active power per chip area
  (P/AREA) 1/tox ? V2 ? f ? s3 2.92----serious
  issue. This puts burden on VLSI packaging
  technology to dissipate extra heat generated on
  the chip
• Active capacitance/unit-areapower density/ (V2
  ? f ) ---? s

EEE C443 Analog and Digital VLSI Design
50
Generalised Scalingto control reliability
problemsdimensions -gt 1/selectric field-gt 1/?
51
(No Transcript)
52
Summary scaling factor ?

• Parameter Constant Field Constant Voltage
• Supply voltage (Vdd) 1/? 1
• Length (L) 1/? 1/?
• Width (W) 1/? 1/?
• Gate-oxide thickness (tox) 1/? 1/?
• Junction depth (Xj) 1/? 1/?
• Substrate doping (NA) ? ?
• Electric field across gate oxide (E) 1 ?
• Depletion layer thickness 1/? 1/?
• Gate area (Die area) 1/?2 1/?2
• Gate capacitance (load) (C) 1/? 1/?
• Drain-current (Idss) 1/? ?
• Transconductance (gm) 1 ?
• Gate delay 1/? 1/?2
• Current density ? ?3
• DC Dynamic power dissipation 1/?2 ?
• Power density 1 ?3
• Power-Delay product 1/?3 1/?

53
SCALING OF CONDUCTORS
CAPACITANCE C C/a RESISTANCE R aR TIME
CONSTANT RC RC CURRENT DENSITY J aJ
54

• R?L/wt---increases R sR
• CeoxA/t------decreases C 1/s C
• Interconnect delay does not scale

EEE C443 Analog and Digital VLSI Design
55

• Interconnects scaling
• Higher densities are only possible if the
  interconnects also scale.
• Reduced width ? increased resistance
• Denser interconnects ? higher parasitic
  capacitance due to mutual coupling
• To account for increased parasitics and
  integration complexity more interconnection
  layers are added
• thinner and tighter layers ? local
  interconnections
• thicker and sparser layers ? global
  interconnections and power
• Interconnects are scaling as expected

EEE C443 Analog and Digital VLSI Design
56
Multilevel Interconnect
57
Scaling Models Long Channel
EEE C443 Analog and Digital VLSI Design
58
Global vs Local wires

• Local wire delay is negligible in comparison to
  global wire.
• 2 reasons--- large length, more functionality-gt
  increased chip area-gt length further increases
• Reducing cross-sectional area (w x t)-gt
• increases resistance , increase current density?
  (electromigration)
• So, do not scale global wires rather scale up.
  This increase capacitance

59
Best strategy for interconnect scaling

• Keep global wires to min.
• Scale down the size and spacing of local wires in
  step with device scaling for local wiring
• Use un-scaled or even scaled up global wires on
  top levels. Use repeaters in global wires,
  increase inter-metal dielectric thickness to keep
  wire capacitance per unit length constant

60
Wiring hierarchy
61
SHORT CHANNEL EFFECTS
62
The Sub-Micron MOS Transistor
63
Threshold Variations
64
Parasitic Resistances
65
Velocity Saturation (1)
66
Velocity Saturation (2)
67
Sub-Threshold Conduction
68
Latchup
69
SPICE MODELS
70
Fitting level-1 model for manual analysis
71
Technology Evolution
72
Process Variations
73
(No Transcript)
74
Impact of Device Variations
75
Latchup