VLSI

1
VLSI

• Prof. Vojin G. Oklobdzija
• References (used for creation of the presentation
  material)
• 1 Mead, Conway, Introduction to VLSI Systems,
  Addison Wesley Publishing.
• 2 Glasser, Dobberpuhl, The Design and Analysis
  of VLSI Circuits, Addison Wesley Publishing.
• 3 Weste, Eshraghian, Principles of CMOS VLSI
  Design, Addison Wesley Publishing.
• 4 Shoji, CMOS Digital Circuits Technology,
  Prentice Hall.

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Historical Overview

• nMOS era 1970-85
• Pass-transistor design
• Domino CMOS, 1982
• NORA
• DCVSL
• CPL, DPL
• DCVS-PG
• SRPL
• LEAP
• SOI-CMOS

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n-MOS Design Era

• LSI started with nMOS
• pass-transistor design experience
• Flourished at the beginning of the nMOS era
• (popularized by Mead-Conway book)
• Allows high density layout and compact design
  style
• Fast outperforming gate based design
• Low in power
• Drawbacks
• Not compatible with existing design tools
• Exhibiting testability and reliability problems

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Pass-Transistor Design

• Another way of looking at Karnaugh Map AND
  function

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Pass-Transistor Design

• Two-variable function

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Pass-Transistor Design

• Threshold Voltage Drop problem

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Pass-Transistor Design

• Solving the Threshold Voltage Drop problem in
  CMOS

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Pass-Transistor Design

• Function Generator

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Pass-Transistor Design

• Full 1-bit Adder

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Pass-Transistor Design

• Compact ALU
• Example
• (IBM PC/RT)
• Circ. 1984

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Control Lines Control Lines Control Lines Control Lines Control Lines Control Lines Control Lines Control Lines Output Control Output Control
A - inputs A - inputs A - inputs A - inputs B - inputs B - inputs B - inputs B - inputs Output Control Output Control
Odd Odd Even Even Odd Odd Even Even Output Control Output Control
Operation Operation K1 K2 Qn A A B B Odd Even
Arithmetic Arithmetic
AB Add 0 0 0 0 1 1 0 0 1 1 0 0 1
AB1 0 0 1 0 1 1 0 0 1 1 0 0 1
A-B Subtract 0 0 1 0 1 1 0 1 0 0 1 0 1
B-A Subtract 0 0 1 1 0 0 1 0 1 1 0 0 1
B1 Increment 0 0 1 1 1 0 0 0 1 1 0 0 1
1 2s compl 0 0 1 1 1 0 0 1 0 0 1 0 1
A1 Increment 0 0 1 0 1 1 0 1 1 0 0 0 1
1 2s compl 0 0 1 1 0 0 1 1 1 0 0 0 1
Logical Logical
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
B B 1 1 0 0 0 0 0 0 1 0 1 0 0
1 1 0 0 0 0 0 1 0 1 0 0 0
1 1 0 0 1 0 1 0 1 0 1 0 0
1 1 0 0 1 0 1 1 0 1 0 0 0
1 1 0 1 0 1 0 0 0 0 0 0 0
1 1 0 1 0 1 0 0 1 0 1 0 0
0 0 1 1 0 0 0 0 0 0 0 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 1
A A 1 1 0 1 0 1 0 0 0 0 0 1 1
1 1 0 0 1 0 1 0 1 0 1 1 1
1 1 0 0 1 0 1 1 0 1 0 1 1
1 1 0 1 0 1 0 0 1 0 1 1 1
0 1 0 0 1 0 1 0 1 0 1 1 1
0 1 0 0 1 0 1 1 0 1 0 1 1
0 1 0 1 0 1 0 0 1 0 1 1 1
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Pass-Transistor Design

• Compact ALU
• Example
• (IBM PC/RT)

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Using Pass-Transistor Design to Speed-up Addition
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Review of CMOS

• Prof. Vojin G. Oklobdzija

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CMOS Basics
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CMOS Basics
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CMOS Basics
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CMOS Basics

• A complex path example

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CMOS Basics
More complex blocks are realizable in CMOS
Primitive gates
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CMOS Deficiencies
Muli-Input NOR function in CMOS is slow
Various remedies
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CMOS Deficiencies and Remedies
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CMOS Deficiencies and Remedies
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CMOS Basic

• Inverter Transfer function
• Logic voltage levels are VOH and VOL
• and VIL and VIH
• The inverter transfer function lie
• within the shaded region

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CMOS Basic Inverter Characteristic
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CMOS Basic Inverter Characteristic
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CMOS Basic Inverter Characteristic

• Transistors during the transition

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CMOS Basic Inverter Switching
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CMOS Basic Power

• During the static state there is no current
• Current is only present during transistion
• Short circuit current (crow-bar current)
• Charging and discharging of the output capacitor
• Leakage Current

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CMOS Basic Power
PCMOSkCLV2DDfo

• This is an Emc2 of low-power design
• There are three ways to control power
• Reducing Power-Supply Voltage (most effective !!)
  
• Reducing the switching activity k (various ways)
• Reducing CL (technology scaling etc.)
• Reducing the required frequency of operation (?)

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CMOS Basic Delay

• Which one of the three designs is the fastest ?
• How can we find this out without simulation ?

Learn about Logical Effort !
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CMOS Basic Delay
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CMOS Basic Delay

• Delay can be approximated with
• RND7Cin1RNORCin2RND2Cout

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CMOS Basic Delay

• Delay of a signal path in CMOS logic is dependent
  on
• Fan-in of a gate
• Represented as a resistance of the pull-up/down
  transistor path of the gate
• Fan-out of a gate
• Represented as a capacitive load at the output
• Number of CMOS blocks in the path.
• Wire delay connecting various blocks.

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CMOS Basic Delay

• Delay of a signal path in CMOS logic can be
  reduced by
• Making the transistors larger in order to
  minimize resistance of a pull-up/down path in the
  gate
• Making the transistors smaller in order to
  minimize the capacitive load of each gate
• Reducing the number of CMOS blocks in the path.
• Bringing the blocks closer and/or choosing the
  less wire intensive topology.
• Note that these requirements are often
  contradictory

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CMOS Basic Delay

• How to estimate delay and critical timing in CMOS
  circuits ?
• How to determine the proper transistor sizing in
  order to make a compromise with contradicting
  requirements ?
• How to choose the right circuit topology ?
• The Answer
• Logical Effort