Advancing Strained Silicon

1
Advancing Strained Silicon

• A ONeill, S Olsen, University of Newcastle
• P-E Hellstrom, M Ostling, KTH
• K Lyutovich, E Kasper, University of Stuttgart

2
Scope

• First investigation of thin VS MOSFETs
• 10x reduction in virtual substrate thickness
• Reduced self-heating
• Reduced growth time
• Compare thin with thick VS MOSFET

3
SiNANO collaboration

• WP1
• Stuttgart
• KTH
• Newcastle

4
Strained Si Material
Growth ID
IL growth T (C)
Processed wafers
A1669
550
A1670
575
T1
A1671
600
A1672
625
A1673
650
T2
A1674
675
Si control
5
Processing

• Device isolation deposited oxide
• Gate oxide 2.8 nm
• Poly-Si 150 nm
• Spacer formation TEOS/Si3N4
• Source/Drain implants As 950 C RTA
• Silicide 20 nm NiSi
• Isolation 200 nm low temperature oxide
• Metalisation TiW (120 nm) and Al (500 nm)

6
nMOSFET

• no cross-hatching or dislocation pile-ups

7
Wafer yield
T2 T1 Si control

• 53.4 89.7 65.5
• yield not determined by material quality
• (yield on Si control is only 65)

Lg 10 mm
8
Short-channel performance
Lg 0.35 mm Vg-Vt 1,2,3 V

• High performance strained Si MOSFETs
• Only small self-heating, despite high Id
• High knee voltage for T2 devices

9
Series resistance silicide
Rsh (ohm/sq) T2 T1
Si control
Minimum 49 10 7 Maximum
99 11 7 Median 69
10 8

• RshSi lt RshT1 lt RshT2
• Same trend for NiSi on gate gt primarily a
  process issue

10
Series resistance contacts
Rc (ohms) T2 T1
Si control
Minimum 42 14 3.8 Maximum
7700 979 15.6 Median 3090
126 8.6

• RcSi ltlt RcT1 ltlt RcT2
• Problems with Al-TiW-NiSi source/drain contacts
  for strained Si wafers

11
FIB investigation of contacts
T1
smooth contact, no overetch
T2
rough contact, much overetch (160 nm)

• Overetch of vias resulting in contact to SiGe
  virtual substrate
• (caused by thin silicide layer reducing etch
  selectivity?)

12
Impact of Rs on short channel performance
Lg 0.35 mm
400
400
T2
T2
350
T1
350
T1
Si control
300
300
Si control
1.0 V (mS/mm)
1.0 V (mS/mm)
250
250
200
maximum transconductance
200
maximum transconductance
150
150
d
d
at V
at V
100
100
max
50
max
50
m
g
m
g
0
0
0
20
40
60
80
100
1
10
100
1000
10000
source/drain sheet resistance R
(ohms/sq)
contact resistance R
(ohms)
sh
C
High Rsh and Rc degrade gmmax
13
Impact of Rs on long channel performance
Lg 10 mm
30
25
1.0 V (mS/mm)
20
1.0 V (mS/mm)
15
maximum transconductance
d
10
at V
T2
T2
T1
5
T1
max
Si-control
Si-control
m
g
0
0
20
40
60
80
100
source/drain sheet resistance R
(ohm/sq)
sh
Little impact of high Rsh and Rc on long channel
performance gt concentrate analysis on large
geometry devices
14
Device performance Ioff dependence on material
Lg 10 mm
T2
Vd 0.1 V
Vd 1.0 V
Vd 0.1 V
T2
T1
T1

• Ioff(T2) gt Ioff(T1) gt Ioff(Si)
• Only T2 wafer exhibits large cross-wafer
  variation in Ioff

15
Cross-wafer variation Ioff
T2 T1 Si control
Vd 0.1 V, Lg 10 mm
16
Sub-threshold summary
Lg 10 mm, Vd 0.1 V
17
Device performance Ioff dependence on Vd
T2
T2
T1
T1
Lg 10 mm

• Both SSi wafers exhibit large dependence of
  Ioff on Vd
• Electrical measurements confirm Ioff dominated by
  substrate current

18
Origin of leakage n/p junction

• n1.45 ? recombination sites
• xj 120 nm? intermediate SiGe layer

19
Origin of leakage defects
T2
T1
100 mm
100 mm
Etch pit density 2.2x106 cm-2
Etch pit density 9x105 cm-2

• Reverse processing on best-performing devices
  (gate regions)
• Schimmel etch consisting of CrO3/HF
• Increased defect density on material grown at T2

20
C-V characteristics
Low T High T Si control

• No difference in EOT between wafers ( 3 nm)
• C-V measurements carried out on 50 mm x 100 mm
  MOS capacitors

21
Gate oxide quality
best 10 mm die best 0.35 mm die
1.E13
1.E13
Median
Median
Best
Best
)
-1
)
eV
-1
eV
-2
1.E12
1.E12
-2
(cm
(cm
it
D
it
D
1.E11
1.E11
T1
T2
Si Control
T1
T2
Si Control

• Regardless of gate length
• No impact of SiGe virtual substrate on Dit
• No correlation between gmmax and Dit!

22
Surface roughness
T2
T1

• AFM measurements carried on 20 mm x 20 mm scan
  areas
• No clear impact of growth T on surface roughness

23
Analysis by Raman Spectroscopy
l 514.5 nm
Si-Si bond in Si substrate
Si-Si bond in Si channel
Si-Si bond in SiGe VS
IL growth T 675 degC

• Raman spectra provide information on Ge
  composition, channel thickness, virtual substrate
  thickness and channel strain.
• Shift in peak for Si-Si in SiGe indicates
  fluctuation in VS Ge composition
• Spectra may also be influenced by defectivity

24
Ge-strain correlation
T1
T2

• As-grown channel stress follows VS Ge
  composition
• Processed channel strain measurements in progress

25
Drain current enhancements
T2 T1 Si
T1 T2

LW10um
Uniform enhancements in Ion with Vd suggest
little self-heating
26
Mobility enhancement 50
27
Device performance gm
Lg 10 mm
T2
T1
Si

Vd 0.1 V
28
Cross-wafer variation gm
30
T2
T1
25
Si
20
15
Count
10
5
0
7
9
11
13
15
17
19
21
23
25
Maximum transconductance gm (mS/mm)
Vd 1.0 V, Lg 10 mm
29
Impact of gate length on gmmax
T1 T2 Si
T1 T2 Si

Vd 0.1 V
Vd 1.0 V

• Expected increases in gmmax at smaller Lg
  observed

30
Impact of gate length on gmmax
Reduced enhancements for high Vd self heating?
31
Impact of gate length on gmmax
Olsen et al, J Appl Phys (2005)
Reduced enhancements for high Vd self
heating? Greater impact of self heating for thick
virtual substrate
32
Impact of gate length on gmmax
Olsen et al, IEEE Trans ED (2003)
Reduced enhancements for high Vd self
heating? Greater impact of self heating for thick
virtual substrate Same increase in enhancement
for low Vd for thick virtual substrate (x0.15)
33
Cut-off frequency vs. gate length
W 5 µm Vd 1.2 V
100 enhancement in cut-off frequency for
strained devices
34
Cut-off frequency vs. gate length
W 5 µm Vd 1.2 V
Lg 1 µm Vd 1.2 V
100 enhancement in cut-off frequency for
strained devices gate width increases cut-off
frequency de-embedded pads (not circuit model)
35
Summary

• First thin virtual substrate MOSFETs
• Enhanced performance
• reduced self heating (cf thick VS)
• RF performance demonstrated