ECE 425 VLSI Circuit Design

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ECE 425 - VLSI Circuit Design

• Lecture 2 - CMOS ProcessingSpring 2007

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• Reading
• Wolf 1, 2.1-2.3

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Where we are...

• Last time
• Course overview
• VLSI Overview
• Today
• CMOS Processing
• Discuss Labs 0, 1

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Roadmap for the term major topics

• VLSI Overview
• CMOS Processing Fabrication
• Components Transistors, Wires, Parasitics
• Design Rules Layout
• Combinational Circuit Design Layout
• Sequential Circuit Design Layout
• Standard-Cell Design with CAD Tools
• Systems Design using Verilog HDL
• Design Project Complete Chip

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N Transistor Structure Review
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P Transistor Structure Review
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Semiconductor Review

• Create by doping a pure silicon crystal
• Diffuse impurity into crystal lattice
• Changes the concentration of carriers
• Electrons
• Holes
• More doping -gt more carriers available
• n-type semiconductor (n or n)
• Majority carrier electrons
• Typical impurity Arsenic (Column V)
• p-type semiconductor (p or p)
• Majority carrier holes
• Typical impurity Boron (Column III)

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Other key working materials

• Insulator - Silicon Dioxide (SiO2)
• Used to insulate transistor gates (thin oxide)
• Used to insulate layers of wires (field oxide)
• Can be grown on Silicon or Chemically Deposited
• Polysilicon - polycrystalline silicon
• Key material for transistor gates
• Also used for short wires
• Added by chemical deposition
• Metal - Aluminum (and more recently Copper)
• Used for wires
• Multiple layers common
• Added by vapor deposition or sputtering

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CMOS Processing

• Wafer Processing
• Photolithography
• Oxide Growth Removal
• Material Deposition Removal
• Diffusion of Impurities
• Putting it all together

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A View of the Cleanroom
AMDs Dresden Fab - Source AMD Corporation
www.amd.com
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Creating Wafers - Czochralski Method

• Start with crucible of molten silicon (1425oC)
• Insert crystal seed in melt
• Slowly rotate / raise seed to form single crystal
  boule
• After cooling, slice boule into wafers polish

Molten Silicon
Crucible
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Wafer Structure

• Current production 200mm
• Newest technology 300mm

300mm wafer Image Source Intel Corporation
www.intel.com
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Processing Wafers

• All dice on wafer processed simultaneously
• Each mask has one image for each die
• The basic approach
• Add selectively remove materials
• Metal - wires
• Polysilicon - gates
• Oxide
• Selectively diffuse impurities
• Photolithography is the key

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Photolithography

• Coat wafer with photoresist (PR)
• Shine UV light through mask to selectively expose
  PR
• Use acid to dissolve exposed PR
• Now use exposed areas for
• Selective doping
• Selective removal of material under exposed PR

Wafer
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Adding Materials

• Add materials on top of silicon
• Polysilicon
• Metal
• Oxide (SiO2) - Insulator
• Methods
• Chemical deposition
• Sputtering (Metal ions)
• Oxidation

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Oxide (Si02) - The Key Insulator

• Thin Oxide
• Add using chemical deposition
• Used to form gate insulator block active areas
• Field Oxide (FOX) - formed by oxidation
• Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
• Used to insulate non-active areas

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Patterning Materials using Photolithography

• Add material to wafer
• Coat with photoresist
• Selectively remove photoresist
• Remove exposed material
• Remove remaining PR

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Diffusion

• Introduce dopant via epitaxy or ion implant e.g.
  Arsenic (N), Boron (P)
• Allow dopants to diffuse at high temperature
• Block diffusion in selective areas using oxide or
  PR
• Diffusion spreads both vertically, horizontally

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CMOS Well Structures

• Need to accommodate both N, P transistors
• Must implement in separate regions - wellls
  (tubs)
• N-well
• P-well
• Alternate approach Silicon on Insulator (SOI)

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Detailed View - N-Well Process

• Overall chip doped as p substrate, tied to GND
• Selected well areas doped n, tied to VDD

Gnd
VDD
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CMOS Processing - Creating an Inverter

• Substrate
• Well
• Active Areas
• Gates
• Diffusion
• Insulator
• Contacts
• Metal

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CMOS Mask Layers

• Determine placement of layout objects
• Color coding specifies layers
• Layout objects
• Rectangles
• Polygons
• Arbitrary shapes
• Grid types
• Absolute (micron)
• Scaleable (lambda)

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Mask Generation

• Mask Design using Layout Editor
• user specifies layout objects on different layers
• output layout file
• Pattern Generator
• Reads layout file
• Generates enlarged master image of each mask
  layer
• Image printed on glass reticle
• Step repeat camera
• Reduces copies reticle image onto mask
• One copy for each die on wafer
• Note importance of mask alignment

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Advanced Fabrication

• Advanced Transistor Fabrication
• Strained Silicon
• Planarization
• Copper Interconnect
• Low-k dielectric for interconnect
• High-k dielectric for transistor gates
• Optical problems (and fixes)
• Immersion Lithography
• Maskless Lithography

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Advanced Transistor Fabrication

• Shallow Trench Isolation (STI) to separate
  transistors - trenches filled with oxide by CVD
• Lightly Doped Drain/Source followed by deeper
  doping
• Silicon Nitride (SiN) - Spacer
• Silicide - refractory metal (e.g. Ti, Pt, W, Ta,
  Co) to reduce resistance of polysilicion and
  diffusion

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Strained Silicon

• Goal Reduce resistance in transistor channel
• Key idea slightly stretch Si crystal lattice

Graphic Source IBM
Graphic Source Intel
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Planarization

• Problem adding multiple layers of metal is
  difficult over uneven chip structures
• Solution Planarization
• Add thick oxide layer over chip
• Use Chemical-Mechanical Polishing (CMP) to grind
  flat

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Copper interconnect

• Copper is a much better conductor than aluminum
• But, it reacts chemically with silicon, oxide
• Fabrication of copper wires damascene process
• Etch trenches in the surface where wires will be
  placed
• Coat with secret chemical (isolates Cu,
  silicon, oxide)
• Coat with layer of copper
• Polish wafer to remove copper except in trenches

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Alternative Dielectrics

• Dielectric constant of SiO2 3.9
• Problem want to minimize coupling capacitance
  between wires
• Solution low-k dielectrics (featured in 130nm
  and below)
• Proposed materials would have approx K3
• But, some of the new materials have been
  difficult to use
• Problem want to maximize electric field under
  transistor gates
• Solution high-k dielectrics (need for 90nm and
  below)
• Proposed materials would have Kgtgt4

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Wiring Examples - Intel Processes
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Optical Problems

• Most photolithography is done using UV with 248nm
  wavelength
• BUT current geometries ltlt 248nm gt interference
  problems
• Fixes
• Optical proximity correction (OPC) - change
  shapes of layout objects to account for optical
  errors
• Phase-shifting masks
• Other light sources 193nmUV, Extreme UV,
  X-Rays(Alternative E-beam lithography)

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Optical Proximity Correction

• Key idea Pre-warp mask patterns to anticipate
  and correct diffraction errors

Image source Forbes Magazine www.forbes.com
Image source Synopsys Corporation
www.synopsys.com
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Example - Phase Shifting Masks

• Normal mask - light spreads overlaps
• Phase shifting mask - cancels overlap
• Drawback requires 2 masks per litho. step
  (Expensive)

Graphic source Numerical Technologies
www.numeritech.com
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Immersion Lithography

• Key idea immerse light source and mask in a
  liquid with a higher index of refraction than air
• Result higher resolution (analogy to microscope
  with oil drop)

Graphic source Nikon
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Maskless Lithography

• Key idea instead of shining UV light through
  mask, expose photoresist directly
• E-Beam - use one or more steerable beams of
  electrons
• Micromirror array - steer light to expose PR
• Imprint lithography - pattern by direct contact
• Intended for low-volume applications

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After Fabrication- Testing and Packaging
Figure Source D. Patterson and J. Hennessey,
Computer Organization and Design, Morgan
Kafumann, 1996
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Coming Up

• Transistor Operation
• More about Wires Contacts
• Parasitics

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Lecture 2 Addendum - Breaking News!

• Intel, IBM, Sematech announce 45nm design process
  (Jan 2007)
• Key feature metal-gate transistors with high-K
  dielectric
• 10X reduction gate oxide leakage current
• 1.2X drive current increase or 5X S-D leakage
  reduction

Image source EE Times www.eetimes.com
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Bottom Line Moores Law Lives!

• Doubled transistor density compared to 65nm
• Penryn - Dual Core, 200M Trans.
• 4-Core, 8-Core chips planned!

Intel Penryn (Image source www.intel.com)