Assign the Lamport

1

• Assign the Lamports logical clock values for all
  the events in the above timing diagram. Assume
  that each processs local clock is set to 0
  initially.

2

• From the above timing diagram, what can you say
  about the following events?
• between a and b a ? b
• between b and f b ? f
• between e and k concurrent
• between c and h concurrent
• between k and h k ? h

3

• Fidges Logical Clocks
• with Lamports clocks, one cannot directly
  compare the timestamps of two events to determine
  their precedence relationship
• - if C(a) lt C(b) then a ? b
• - if C(a) lt C(b), it could be a ? b or a ? b
• - e.g, events e and b in Figure previous page
• C(e) 1 and C(b) 2
• thus C(e) lt C(b) but e ? b
• the main problem is that a simple integer clock
  can not order both events within a process and
  events in different processes
• C. Fidge developed an algorithm that overcomes
  this problem
• Fidges clock is represented as a vector c1 , c
  2 , , cn with an integer clock value for each
  process (ci contains the clock value of process
  i).

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4

• Fidges Algorithm
• The Fidges logical clock is maintained as
  follows
• FLC1 Initially all clock values are set to the
  smallest value.
• FLC2 The local clock value is incremented at
  least once before each primitive event in a
  process.
• FLC3 The current value of the entire logical
  clock vector is delivered to the receiver for
  every outgoing message.
• FLC4 Values in the timestamp vectors are never
  decremented.
• FLC5 Upon receiving a message, the receiver sets
  the value of each entry in its local timestamp
  vector to the maximum of the two corresponding
  values in the local vector and in the remote
  vector received. The element corresponding to the
  sender is a special case it is set to one
  greater than the value received, but only if the
  local value is not greater than that received.

5

• Get r_vector from the received msg sent by
  process q
• if l_vector q ? r_vectorq then
• l_vectorq r_vectorq 1
• for i 1 to n do
• l_vectori max(l_vectori, r_vectori)
• Timestamps attached to the events are compared as
  follows
• ep ? fq iff Tep p lt Tfq p
• (where ep represents an event e occurring in
  process p, Tep represents the timestamp vector of
  the event ep , and the ith element of Tep is
  denoted by Tep i.)
• This means event ep happened before event fq if
  and only if process q received a direct or
  indirect message from p and that message was sent
  after ep had occurred. If ep and fq are in the
  same process (i,e., p q), the local elements of
  their timestamps represent their occurrences in
  the process.

6

• Assign the Lamports and Fidges logical clock
  values for all the events in the above timing
  diagram. Assume that each processs logical clock
  is set to 0 initially.

7
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8

• The above diagram shows both Lamport timestamps
  (an integer value ) and Fidge timestamps (a
  vector of integer values ) for each event.
• Lamport clocks
• 2 lt 5 since b ? h,
• 3 lt 4 but c ? g.
• Fidge Clocks
• f ? h since 2 lt 4 is true,
• b ? h since 2 lt 3 is true,
• h ? a since 4 lt 0 is false,
• c ? h since (3 lt 3) is false and ( 4lt0) is false.

9

• Assign the Lamports and Fidges logical clock
  values for all the events in the above timing
  diagram.

10

• READING Reference
• Colin Fidge, Logical Time in Distributed
  computing systems, IEEE Computer, Vol. 24, No.
  8, pp. 28-33, August 1991.