Pengantar Organisasi Komputer

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IKI20210Pengantar Organisasi KomputerKuliah No.
23 Aritmatika
Sumber1. Hamacher. Computer Organization,
ed-4.2. Materi kuliah CS61C/2000 CS152/1997,
UCB.
18 Desember 2002 Bobby Nazief (nazief_at_cs.ui.ac.id)
Johny Moningka (moningka_at_cs.ui.ac.id) bahan
kuliah http//www.cs.ui.ac.id/iki20210/
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• Number Representation

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Decimal vs. Hexadecimal vs.Binary
Unsigned Numbers Dec Hex Binary 00 0 000001 1 000
102 2 001003 3 001104 4 010005 5 010106 6 011
007 7 011108 8 100009 9 100110 A 101011 B 101
112 C 110013 D 110114 E 111015 F 1111

• Decimalgreat for humans, especially when doing
  arithmetic
• Hexif human looking at long strings of binary
  numbers, its much easier to convert to hex and
  look 4 bits/symbol
• Terrible for arithmetic just say no
• Binarywhat computers use you learn how
  computers do ,-,,/
• To a computer, numbers always binary

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How to Represent Negative Numbers?

• So far, unsigned numbers
• Obvious solution define leftmost bit to be sign!
  
• 0 gt , 1 gt -
• Rest of bits can be numerical value of number
• Representation called sign and magnitude

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Shortcomings of sign and magnitude?

• Arithmetic circuit more complicated
• Special steps depending whether signs are the
  same or not
• Also, Two zeros
• 0x00000000 0ten
• 0x80000000 -0ten
• What would it mean for programming?
• Sign and magnitude abandoned

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Another try complement the bits

• Example 710 001112 -710 110002
• Called ones Complement
• Note postive numbers have leading 0s, negative
  numbers have leadings 1s.

• What is -00000 ?
• How many positive numbers in N bits?
• How many negative ones?

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Shortcomings of ones complement?

• Arithmetic not too hard
• Still two zeros
• 0x00000000 0ten
• 0xFFFFFFFF -0ten
• What would it mean for programming?
• Ones complement eventually abandoned because
  another solution was better

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Search for Negative Number Representation

• Obvious solution didnt work, find another
• What is result for unsigned numbers if tried to
  subtract large number from a small one?
• Would try to borrow from string of leading 0s,
  so result would have a string of leading 1s
• With no obvious better alternative, pick
  representation that made the hardware simple
  leading 0s ? positive, leading 1s ? negative
• 000000...xxx is gt0, 111111...xxx is lt 0
• This representation called twos complement

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Twos Complement Number line
00000
11111
00001

• 2 N-1 non-negatives
• 2 N-1 negatives
• one zero
• how many positives?
• comparison?
• overflow?

11110
00010
0
-1
1
2
-2
. . .
. . .
15
-15
-16
01111
10001
10000
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Twos Complement Numbers

• 0000 ... 0000 0000 0000 0000two
  0ten0000 ... 0000 0000 0000 0001two
  1ten0000 ... 0000 0000 0000 0010two
  2ten. . .0111 ... 1111 1111 1111 1101two
  2,147,483,645ten0111 ... 1111 1111 1111
  1110two 2,147,483,646ten0111 ... 1111 1111
  1111 1111two 2,147,483,647ten1000 ... 0000
  0000 0000 0000two 2,147,483,648ten1000 ...
  0000 0000 0000 0001two 2,147,483,647ten100
  0 ... 0000 0000 0000 0010two
  2,147,483,646ten. . . 1111 ... 1111 1111
  1111 1101two 3ten1111 ... 1111 1111 1111
  1110two 2ten1111 ... 1111 1111 1111
  1111two 1ten
• One zero, 1st bit gt gt0 or lt0, called sign bit
• but one negative with no positive
  2,147,483,648ten

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Twos Complement Formula

• Can represent positive and negative numbers in
  terms of the bit value times a power of 2
• d31 x -231 d30 x 230 ... d2 x 22 d1 x 21
  d0 x 20
• Example1111 1111 1111 1111 1111 1111 1111
  1100two
• 1x-231 1x230 1x229... 1x220x210x20
• -231 230 229 ... 22 0 0
• -2,147,483,648ten 2,147,483,644ten
• -4ten
• Note need to specify width we use 32 bits

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Twos complement shortcut Negation

• Invert every 0 to 1 and every 1 to 0, then add 1
  to the result
• Sum of number and its ones complement must be
  111...111two
• 111...111two -1ten
• Let x mean the inverted representation of x
• Then x x -1 ? x x 1 0 ? x 1 -x
• Example -4 to 4 to -4x 1111 1111 1111 1111
  1111 1111 1111 1100twox 0000 0000 0000 0000
  0000 0000 0000 0011two1 0000 0000 0000 0000
  0000 0000 0000 0100two() 1111 1111 1111 1111
  1111 1111 1111 1011two1 1111 1111 1111 1111
  1111 1111 1111 1100two

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Twos comp. shortcut Sign extension

• Convert 2s complement number using n bits to
  more than n bits
• Simply replicate the most significant bit (sign
  bit) of smaller to fill new bits
• 2s comp. positive number has infinite 0s
• 2s comp. negative number has infinite 1s
• Bit representation hides leading bits sign
  extension restores some of them
• 16-bit -4ten to 32-bit
• 1111 1111 1111 1100two
• 1111 1111 1111 1111 1111 1111 1111 1100two

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• Addition of Positive Numbers

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One-Bit Full Adder (1/3)

• Example Binary Addition

• Thus for any bit of addition
• The inputs are ai, bi, CarryIni
• The outputs are Sumi, CarryOuti
• Note CarryIni1 CarryOuti

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One-Bit Full Adder (2/3)
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One-Bit Full Adder (3/3)

• To create one-bit full adder
• implement gates for Sum
• implement gates for CarryOut
• connect all inputs with same name

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Ripple-Carry Adders adding n-bits numbers
CarryIn0
A0
1-bit FA
Sum0
B0
CarryOut0
CarryIn1
A1
1-bit FA
Sum1
B1
CarryOut1
CarryIn2
A2
1-bit FA
Sum2
B2
CarryOut2
CarryIn3
A3
1-bit FA
Sum3
B3
CarryOut3

• Critical Path of n-bit Rippled-carry adder is
  nCP
• CP 2 gate-delays (Cout AB ACin BCin)

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Overflow

• Binary bit patterns above are simply
  representatives of numbers
• Numbers really have an infinite number of digits
• with almost all being zero except for a few of
  the rightmost digits
• Just dont normally show leading zeros
• If result of add (or -,/) cannot be represented
  by these rightmost HW bits, overflow is said to
  have occurred
• When CarryOut is generated from MSB

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• Fast Adders

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Carry Look Ahead reducing Carry Propagation delay
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Carry Look Ahead Delays

• Expression for any carry
• Ci1 Gi PiGi-1 PiPi-1 P0C0
• All carries can be obtained in 3 gate-delays
• 1 needed to developed all Pi and Gi
• 2 needed in the AND-OR circuit
• All sums can be obtained in 6 gate-delays
• 3 needed to obtain carries
• 1 needed to invert carry
• 2 needed in the AND-OR circuit of Sums circuit
• Independent of the number of bits (n)
• 4-bit Adder
• CLA 6 gate-delays
• RC (32 3) gate-delays

• 16-bit Adder
• CLA 6 gate-delays
• RC (152 3) gate-delays

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Cascaded CLA overcoming Fan-in constraint
C0
G0
P0
C1 G0 C0 P0
Delay 3 2 3 8 DelayRC 152 3 33
C2 G1 G0 P1 C0 P0 P1
C3 G2 G1 P2 G0 P1 P2 C0 P0 P1
P2
G
P
C4 . . .
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• Signed Addition Subtraction

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Addition Subtraction Operations

• Subtraction
• Form 2s complement of the subtrahend
• Add the two numbers as in Addition

• Addition
• Just add the two numbers
• Ignore the Carry-out from MSB
• Result will be correct, provided theres no
  overflow

0 1 0 1 (5)0 0 1 0 (2) 0 1 1 1 (7)
0 1 0 1 (5)1 0 1 0 (-6) 1 1 1 1 (-1)
0 0 1 0 (2) 0 0 1 0?0 1 0 0 (4) 1 1 0
0 (-4) 1 1 1 0 (-2)
1 0 1 1 (-5)1 1 1 0 (-2)11 0 0 1 (-7)
0 1 1 1 (7)1 1 0 1 (-3)10 1 0 0 (4)
1 1 1 0 (-2) 1 1 1 0?1 0 1 1 (-5) 0 1 0
1 (5) 10 0 1 1 (3)
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Overflow
2s Complement
Binary
Decimal
Decimal
0
0000
0000
0
1
0001
1111
-1
2
0010
1110
-2
3
0011
1101
-3
4
0100
1100
-4
5
0101
1011
-5
6
0110
1010
-6
7
0111
1001
-7
1000
-8

• Examples 7 3 10 but ...
  
• - 4 ? 5 - 9 but ...

1
1
1
0
1
0
1
1
1
1
1
0
0
7
4
3
5
0
0
1
1

1
0
1
1

1
0
1
0
0
1
1
1
6
7
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Overflow Detection

• Overflow the result is too large (or too small)
  to represent properly
• Example - 8 lt 4-bit binary number lt 7
• When adding operands with different signs,
  overflow cannot occur!
• Overflow occurs when adding
• 2 positive numbers and the sum is negative
• 2 negative numbers and the sum is positive
• On your own Prove you can detect overflow by
• Carry into MSB Carry out of MSB

1
1
1
0
1
0
0
1
1
1
1
1
0
0
7
4
3
5
0
0
1
1

1
0
1
1

1
0
1
0
0
1
1
1
6
7
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Overflow Detection Logic

• Carry into MSB Carry out of MSB
• For a N-bit Adder Overflow CarryInN - 1 XOR
  CarryOutN - 1

CarryIn0
A0
1-bit FA
Result0
X
Y
X XOR Y
B0
0
0
0
CarryOut0
0
1
1
1
0
1
1
1
0
CarryIn2
A2
1-bit FA
Result2
B2
CarryIn3
Overflow
A3
1-bit FA
Result3
B3
CarryOut3