Sequential circuit blocks

1
Sequential circuit blocks

• (Verilog)
• 3/12/09

2
Outline

• Verilog for latch
• Edge-sensitive always block
• Verilog for flip-flops
• No-blocking assignments
• Verilog for asyn and syn reset
• Verilog for registers

3
Verilog for Latch
module D_latch (D, Clk, Q) input D,
Clk output Q reg Q always _at_(D or
Clk) if (Clk) Q D endmodule
Clk
D
Q
t
1

(
)
0
x
Q
t
(
)
1
0
0
1
1
1
D
Q
Q
Clk
No else clause Sensitivity list should include D
and Clk
4
always block (overview)

• Level-sensitive always block
• always _at_ (signal1 or signal2)
• Used for combinational circuits and Latches
• Edge-sensitive always block
• always _at_ (posedge clk)
• Response to positive edge of clk signal
• always _at_ (negedge clk)
• Response to negative edge of clk signal
• Used for sequential circuits and flip-flops

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D flip-flop
module flipflop (D, Clock, Q) input D,
Clock output Q reg Q always _at_(posedge
Clock) Q D endmodule
Sensitivity list contains only Clock Why?
6
Assignments (overview)

• Continuous assignments fixed connection
• assign f1 a b
• assign f2 f1
• Blocking assignments evaluate in order
• in always block
• begin
• Q1 D // new Q1 will be used in
  evaluating all subsequent statements in this
  block
• Q2 Q1 // new Q1 goes to Q2, so Q2 is
  equal to D.
• end
• No-blocking assignments evaluate in parallel
• lt in always block
• begin
• Q1lt D
• Q2lt Q1 // old Q1 goes to Q2
• End
• The order of statements doesnt matter

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Blocking and non-blocking assignments
Initially, Q110, Q20
Initially, Q110, Q20
always _at_ ( posedge clk) begin Q1 Q2 Q2 Q1
end
always _at_ ( posedge clk) begin Q1 lt Q2 Q2 lt
Q1 end
After one clk positive edge
After one clk positive edge
What happens if we change the order of two
statements?
Q10, Q20
Q10, Q210
?
Q1Q2
Q1,Q2 exchange
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Blocking assign
module example7_3 (D, Clock, Q1, Q2) input D,
Clock output Q1, Q2 reg Q1, Q2 always
_at_(posedge Clock) begin Q1 D Q2
Q1 end endmodule
9
Two cascaded flip-flops
No-blocking assignments
module example7_4 (D, Clock, Q1, Q2) input D,
Clock output Q1, Q2 reg Q1, Q2 always
_at_(posedge Clock) begin Q1 lt D Q2 lt
Q1 end endmodule
10
Example 7.5 (blocking)
module example7_5 (x1, x2, x3, Clock, f,
g) input x1, x2, x3, Clock output f, g reg
f, g always _at_(posedge Clock) begin f x1
x2 g f x3 end endmodule
?
How about reversing the statements f and g?
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Example 7.6 (no-blocking)
module example7_6 (x1, x2, x3, Clock, f,
g) input x1, x2, x3, Clock output f, g reg
f, g always _at_(posedge Clock) begin f lt x1
x2 g lt f x3 end endmodule
12
Recommendations

• It is better to use blocking assignments when
  describing combinational circuits
• It is better to using no-blocking assignments to
  describe sequential circuits

13
T flip-flop
(
)
T
Q
t
1

module tff(t, clk,q) input t, clk output
q reg q always _at_ (posedge clk) case(t) 0
q lt q 1 q lt q endcase endmodule
0
Q
t
(
)
1
Q
t
(
)
(b) Truth table
Q
T
Q
(c) Graphical symbol
14
Quiz write code for J-K ff
K
Q
t
1

(
)
J
0
Q
t
(
)
0
J
Q
1
0
0
0
1
1
Q
K
1
Q
t
(
)
1
(b) Truth table
(c) Graphical symbol
15
Flip-flop with clear capability
module flipflop (D, Clock, Resetn, Q) input D,
Clock, Resetn output Q reg Q always
_at_(negedge Resetn or posedge Clock) if
(!Resetn) Q lt 0 else Q lt
D endmodule
Asynchronous reset by using sensitivity list and
if-else
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Flip-flop with clear capability
module flipflop (D, Clock, Resetn, Q) input D,
Clock, Resetn output Q reg Q always
_at_(posedge Clock) if (!Resetn) Q lt 0 else
Q lt D endmodule 
Synchronous reset by using if-else
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N-bit register
module regn (D, Clock, Resetn, Q) parameter n
16 input n-10 D input Clock,
Resetn output n-10 Q reg n-10
Q   always _at_(negedge Resetn or posedge Clock)
if (!Resetn) Q lt 0 else Q lt
D endmodule
Dn-1
Qn-1
Q
D
Q
D
D0
Q0
Q
D
Clock
18
4-bit shift register
module shift4 (R, L, w, Clock, Q) input 30
R input L, w, Clock output 30 Q wire
30 Q   muxdff Stage3 (w, R3, L, Clock,
Q3) muxdff Stage2 (Q3, R2, L, Clock,
Q2) muxdff Stage1 (Q2, R1, L, Clock,
Q1) muxdff Stage0 (Q1, R0, L, Clock,
Q0)   endmodule
module muxdff (D0, D1, Sel, Clock, Q) input D0,
D1, Sel, Clock output Q reg Q   always
_at_(posedge Clock) if (!Sel) Q lt D0 else
Q lt D1 endmodule
Q
Circuit ?
D
clock
sel
0 1
D0
D1