Title: Apresenta
1C2 Part 4 VLSI CAD Tools Problems and Algorithms
Marcelo Johann
EAMTA 2006
2Outline
- THIRD PART
- Layout Compaction
- Logic Synthesis, BDDs
- Technology Mapping
- Simmulation vs Formal Verification
- Voltage Drop by Random Walks
- FOURTH PART
- High-Level Synthesis
- CDFG, Allocation, Scheduling, Generation
3Function representations
- Truth Tables
- Lists the output for every input combination
- For n variables, 2n lines
- Formulas
- Fx1.x2.x5 x3(x2.x4.x5 x2) x2.x3
- Not Canonical in general, canonical is large
- BDDs
- A graph that packs a truth table
- Average sized, powerful representation
4BDDs
Source Wikipedia
5BDD - good ordering
BDD graph for the Boolean formula x1 x2 x3
x4 x5 x6 x7 x8 using a good variable
ordering
6BDD - bad ordering
BDD graph for the Boolean formula x1 x2 x3
x4 x5 x6 x7 x8 using a bad variable
ordering
7Random Walks
8Random Walks
9IR Drop
10Random Walk
11The Algorithm
- Initialize
- Compute conductance, px,i , mx
- For each node in the circuit
- Loop n times according to accuracy
- Loop until reaching Supply
- Add this nodes cost
- Random select the next move
- Make this node a new supply
- Print the result
12Accuracy
15876 VDD nodes 15625 GND nodes 1.2V Linux 2.8GHz
CPU Delta controls error such that 99 of the
nodes have less then Error Margin
13Jump to
VLSI System DesignPart V High-Level Synthesis
Lecturer Tsuyoshi Isshiki VLSI Design and
Education Center, The University of Tokyo Dept.
Communication and Integrated Systems, Tokyo
Institute of Technology isshiki_at_vlsi.ss.titech.ac.
jp http//www.vlsi.ss.titech.ac.jp/isshiki/VLSISy
stemDesign/top.html
14C2 VLSI CAD Tools Problems and Algorithms
Thank you!
EAMTA 2006