Slice Card Test Stand System

1
Slice Card Test Stand System

• Guilherme Cardoso
• CD/CEPA/ESE
• SNAP Collaboration Meeting, December 2nd,2005

2
Objectives

• Test slice cards as they become available early
  2006
• Develop and prototype system architecture to
  understand
• Scope of the parts in the system
• Communication links, bandwidth requirements,
  logic implementation of algorithms
• Code parts of the system in portable and reusable
  hardware descriptive language
• In the first system testing phase, use as much as
  possible existing hardware
• Second phase will be realized with specific
  hardware.

3
System Architecture
DATA
CONTROLS
DATA
CONTROLS
4
1st Test System
PTA Detector Emulator
PTA Detector Emulator
PTA ICU Interface
PCI Bus
PCI Bus
PC
5
HW, SW, FW Implementation

• PTA Hardware
• PTA and Slice Software and Firmware reuse BTeV,
  CMS and SNAP code.

6
HW, SW, FW Implementation

• Slice Hardware
• Modular design reduces overall system cost
• Fewer layers for the 6U VME motherboard.
• Higher density PCB for daughtercards.
• Flexible use of components.
• Testability of individual components is greatly
  improved.
• Schedule is relaxed since we can test each card
  and its functionalities before the whole system
  is completed.

7
HW, SW, FW Implementation

• Motherboard
• Power Distribution
• Routing for board to board communications
• FLASH and SDRAM (rad hard)
• FPGA are mounted on daughter cards (DC)
• FLASH and SDRAM (commercial)
• Logic Analyzer interface
• DC model 1
• Reprogrammable (for code development)
• DC model 2
• One Time Programmable (for device testing)

8
Daughter Cards
Reprogrammable
OTP
Test Connector
Test Connector
JTAG Header
JTAG Header
FLASH
FLASH
FPGA ProASIC
FPGA AX2000
SDRAM
SDRAM
FPGA Board Connector
FPGA Board Connector
Logic Analyzer Header
Logic Analyzer Header
9
System Test Concept
Motherboard
Backplane Connectors
10
Summary

• First system wide test of SNAP DAQ is under way
  and on schedule for delivery early 2006
• Test system will allow us to better understand
• Hardware/firmware/software code distribution in
  the system
• Thermal issues with FPGA
• Technology choices for FPGA and memories
• Algorithm performance requirements
• Code written in portable hardware descriptive
  language
• Goals will be achieved by leveraging previous
  work to minimize the necessary hw/sw/fw
  development time.