Total Ionizing Dose Effects in Bulk Technologies and Devices

1
Total Ionizing Dose Effects in Bulk Technologies
and Devices

• Hugh Barnaby, Jie Chen, Ivan Sanchez
• Department of Electrical Engineering
• Ira A. Fulton School of Engineering
• Arizona State University

2
Outline

• Overview of ASU tasks
• Total ionizing dose defect models
• Device TID response
• Drain-to-source leakage
• Inter-device leakage
• Analysis of defect buildup across oxide
  structure and between technologies
• Other work

3
ASU task

• Characterize and model TID effects in modern
  devices, primarily CMOS transistors
• Technologies deep sub-micron bulk CMOS, and
  silicon on insulator, general isolations

4
ASU task

• Characterize and model TID effects in modern
  devices, primarily CMOS transistors
• Technologies deep sub-micron bulk CMOS, and
  silicon on insulator, general isolations

In Year 1, we have primarily focused
ondeep-sub-micron bulk CMOS and
generalisolation technologies.
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Primary TID Threat
TID defect build-up in the thick shallow trench
isolation (STI)
Defects

• Not - oxide trapped charge (E )
• Nit interface traps (Pb)

Both Nit and Not are related to holesgenerated
and/or hydrogen present inoxide
first orderassumption
Not, Nit a tox
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Model for Not buildup
After Fleetwood et al. TNS 1994
Model Parameters
D - total dose rad kg - 8.1 x 1012
ehp/radcm3 fy - field dependent hole yield
hole/ehp fot - trapping efficiency trapped
hole/hole tox - oxide thickness cm
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Hole trapping processes
- surviving hole (p)

- hole trap (NT)
- trapped hole (Not)

fp
- hole flux
area s(e)
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Simple analytical model (Not)
(steady state)
(fp gt 0 for all x)
fot
D
(No saturation or annealingand traps at
interface)
After Rashkeev et al. TNS 2002
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Model for Nit buildup
After Rashkeev et al. TNS 2002
Model Parameters
D - total dose rad kg - 8.1 x 1012
ehp/radcm3 fy - field dependent hole yield
hole/ehp fDH - hole, DH reaction efficiency
H/hole fit - H, SiH de-passivation efficiency
interface trap/H tox - oxide thickness cm
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De-passivation processes
- hydrogen defect (DH)
- protons
H
- Si-H (NSiH)
H
- dangling bond (Nit)
- proton flux
fH
area sit
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De-passivation processes
(steady state)
(fH gt 0 for all x)
D
fit
(No saturation or annealingand traps at
interface)
After Rashkeev et al. TNS 2002
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Leakage paths
Defect build-up in STI creates leakage paths in
CMOS ICs.
NMOS Drain-to-Source
1
NMOS D/S to NMOS S/D
2
3
NMOS D/S to NWELL
3
2
1
2 and 3 are inter-device leakage
CMOS inverters
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NMOS drain-to-source leakage
Increasingtotal dose
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Parasitic leakage model

• Parasitic edge device modeled as MOSFET
  operating in parallel with as drawn FET.
• Effective parameters for edge device are
  extracted from data.

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Extracting electrical characteristics
IDedge(post) IDtotal(post) IDtotal(pre)
IDtotal(post)

• Two assumptions
• IDtotal(pre) IDas-drawn(pre)
• IDas-drawn(post) IDas-drawn(pre)

IDedge(post)
IDtotal(pre)
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Edge Capacitor
Prior to radiation exposure, the MOS capacitor
of the edge device has small dimensions, W and
tox
a tox-eff
Weff



STI

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Edge Capacitor
Upon radiation exposure, the edge capacitor is
degradedand the dimensions enlarged.
a tox-eff
Weff




STI


a tox-eff
Weff






Increasingtotal dose
STI

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Edge Capacitor
Increased defect buildup in theSTI sidewall
leads to further increases in W and tox, until
inherent limitations are met.
a tox-eff
Weff




STI


a tox-eff
Weff






Increasingtotal dose




STI







a tox-eff


Weff









STI

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2D simulations
Simulations show how increased Not along sidewall
increases the width of the channel and the
capacitor thickness
Weff
Weff
Weff
Not 21012 cm-2
Not 51012 cm-2
Not 71012 cm-2
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New Test Structure
Devices designed by Faccio and fabricated at
STMicro enable measurements on sidewall
capacitor.

• 90 um

Pre-rad

• 1.3 um

overlap
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Parameter extraction

• Weff increases withTID (increased strong -inv
  current)
• Not and Nit increase with TID (shift in
  threshold voltage)
• Nit and tox increasewith TID (reducedsubthreshol
  d slope)
• Not increasewith TID (shifts inmidgap voltages)

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Simultaneous equations
1. 2. 3. 4.
Solving simultaneouslyenables extraction
of parameters and defectlevels at each TID value
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Parameters and sidewall defects
Parameters
Defects
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Inter-device leakage
n D/S to n-well
n D/S to n D/S
Charge build-upin STI base
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Field oxide transistors
n-well
Metal 1
n D/S
n
n




STI
-
n D/S
Metal 1
noise floor
n-well
130 nm bulk CMOS
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Field oxide capacitors
Single cell
130 nm data

• 1500 Single Cell FOXCAPs in parallel
• gate area of individual cell 7.4 µm x 11.4 µm

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Defect build-up in STI base

• Defect build-up is
• Greater for higher oxidefields (consistent w/
  fy)
• Linear with dose(no saturation yet)

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Comparison to other isolation technologies (Not)
data taken after 20 krad(SiO2) exposures
radiation bias is 0V for all devices
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Sidewall vs. Base Comparison (Not)
Indicates saturation in defect buildup
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Sidewall vs. Base Comparison (Nit)
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Other Work

• Separation of switch state defects in thick
  isolationoxides using frequency dependent charge
  pumping
• Packaging issues

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Gate sweep data
Nss
Nss
Increased current is caused by switching state
buildup (Nss) whichis composed of both interface
and border traps
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Separation of Switching States
Indicates border traps
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Packaging Issues

• Recent testing showed 3x increase in Nit in GLPNP
  devices packaged with sealed gold plated kovar
  lids than packages with taped-on lids.

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Its a hydrogen problem

• As sealed lid is removed, H2 moves quickly out of
  the package and a concentration gradient is
  established for the remaining H2 in the oxide to
  diffuse out, thus reducing Nit generation.

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Another time dependent process
Results shows time dependence of Nit build-up
related hydrogen out diffusion we are working
on the rate equations for this