State Diagrams, Verilog for Sequential

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State Diagrams,Verilog for Sequential

• Anselmo Lastra

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Reminder

• Test next Tuesday

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Topics

• Lab preview
• State tables and diagrams
• Verilog for sequential design
• Review

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Lab Preview

• Digital lock
• Will provide code for slowing clock
• Next

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Counter

• module cntr32(clk, res, out)
• input clk
• input res
• output out
• reg 310 count
• always _at_ (posedge res or posedge clk)
• if(res)
• count lt 0
• else
• count lt count 1
• assign out count22
• endmodule

What does this do?
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Button and Debouncing

• Button normally high
• Mechanical switches bounce
• Go H and L a number of times
• Our circuit debounces

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Flip-Flop for pushbutton

• module button_test(clk, btn, q)
• input clk
• input btn
• output q
• reg q
• always _at_ (posedge clk)
• begin
• if(btn 1)
• q lt 1
• else
• q lt 0
• end
• endmodule

What is this?
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Simple Module for an Example

• module led_on(clk, button, s6)
• input clk
• input button
• output s6
• wire clkb
• cntr32 C1(clk, 0, clkb)
• button_test B1(clkb, button, s6)
• endmodule

• clk to board clock, P88
• button to pushbutton, P93
• Why button?
• s6 to one of LED segments

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Things to Think About

• Can I press button and not light LED?
• What happens if I hold button down for a long
  time?
• What effect will changing period of clkb have?
• On LED
• On button debouncing

Send answers for homework. Due Thursday, 2/13
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Back to Sequential Circuits

• Last time talked about current state and next
  state
• Made tables

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State Diagram

• Alternative representation for state table
• Moore-gt

Inputs
State/Output
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Mealy Model

• Out depends on in and state

Input/Output
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State Table vs. Diagram

• Same information
• Table is perhaps easier to fill in from
  description
• Diagram is easier for understanding and writing
  code
• You can label states with English description
• Eliminate repetitive portions (for example, when
  reset is an input)

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Design Procedure

• Take problem description and refine it into a
  state table or diagram
• Assign codes to the states
• Write Verilog
• See example in a moment
• Designing with gates and FFs more involved
  because you have to derive input and output
  functions

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Example Sequence Recognizer

• Circuit has input, X, and output, Z
• Recognizes sequence 1101 on X
• Specifically, if X has been 110 and next bit is
  1, make Z high

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How to Design States

• States remember past history
• Clearly must remember weve seen 110 when next 1
  comes along
• Tell me one necessary state

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Beginning State

• Some state, A
• If 1 appears, move to next state B

Input / Output
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Second 1

• New state, C
• To reach C, must have seen 11

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Next a 0

• If 110 has been received, go to D
• Next 1 will generate a 1 on output Z

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What else?

• What happens to arrow on right?
• Must go to some state.
• Where?

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What Sequence?

• Here we have to interpret problem
• Weve just seen 01
• Is this beginning of new 1101?
• Or do we need to start over w/ another 1?
• They decide that its beginning (01)

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Cover every possibility

• Well, must have every possibility out of every
  state
• In this case, just two X 0 or 1
• You fill in other cases on board
• Lift screen
• Next slide

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Fill in
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Answer From Book
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State Minimization

• When we make state diagram, do we need all those
  states?
• Some may be redundant
• State minimization procedures can be used
• We wont cover

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State Table

• Just fill in from diagram if need it
• I find diagram more useful

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How to code in Verilog

• Instead of learning how to hand design (Sections
  4-6 and 4-7)
• Learn how to code this in Verilog

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Verilog Case Statement

• Similar to sequence of if/then/else
• case (expression)
• case statements
• other case statements
• default statements // optional
• endcase
• Example in a moment

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Parameter Just Shorthand

• module seq_rec_v(CLK, RESET, X, Z)
• input CLK, RESET, X
• output Z
• reg 10 state, next_state
• parameter A 2'b00, B 2'b01,
• C 2 'b10, D 2'b11

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Next State

• always _at_(X or state)
• begin
• case (state)
• A if (X 1)
• next_state lt B
• else
• next_state lt A
• B if(X) next_state lt Celse next_state lt
  A
• C if(X) next_state lt Celse next_state lt
  D
• D if(X) next_state lt Belse next_state lt
  A
• endcase
• end

The last 3 cases do same thing. Just sparse
syntax.
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On Reset or CLK

• always _at_(posedge CLK or posedge RESET)
• begin
• if (RESET 1)
• state lt A
• else
• state lt next_state
• end

Notice that state only gets updated on posedge of
clock (or on reset)
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Output

• always _at_(X or state)
• begin
• case(state)
• A Z lt 0
• B Z lt 0
• C Z lt 0
• D Z lt X ? 1 0
• endcase
• end

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Comment on Book Code

• Could shorten
• Dont need next_state stored, for example
• Dont need three always clauses

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Review

• Test will be open book, notes, and calculator
• No computer (no ModelSim, etc)
• Chapter 1
• Binary and hexadecimal numbers
• Binary addition, etc.
• Parity

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Review

• Chapter 2
• Boolean algebra
• Schematic diagrams
• Simplification
• Karnaugh maps
• Making circuits from maps
• Nothing on logic families
• Gate delays

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Review

• Chapter 3
• Circuit analysis
• Know what encoder, decoder, and mux are
• Adders
• Signed arithmetic
• How to express positive and negative numbers
• Verilog styles (structural, dataflow, behavioral)
• Be able to write short Verilog programs

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Review

• Chapter 4
• Less emphasis since we havent done problems
• What are latches and flip-flops
• You can look up state in book, no need to
  memorize
• State tables
• State diagrams

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Next Thursday

• Registers and Counters