Asynchronous Logic Design

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Asynchronous Logic Design
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A History

• Most early computers used some kind of central
  clock.
• Exceptions included
• ORDVAC built at the University of Illinois.
• IAS built by John von Neumann's group at the
  Institute for Advanced Study at Princeton
  University.
• Both these machines were first operational in
  1951-52.

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Ruled by the Clock

• Synchronous Systems
• All state changes occur on the clock edge.
• Verification need only ensure timing met between
  registers.
• Requires that all registers see the clock at the
  same time (or a close approximation thereof).
• CMOS gates burns a lot of power when switching.
  The clock tree therefore consumes a lot of power.

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Asynchronous Design

• It is a common misconception to view
  asynchronous design as a single alternative to
  synchronous design. It is more accurate to view
  synchronous design as a special case representing
  a single point in a multi-dimensional
  asynchronous design space.

Source Steve Furber, Cambridge Advanced
Processor Group http//www.cs.man.ac.uk/async/back
ground/return_async.html
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Asynchronous Design Choices

• However there are some binary choices within
  asynchronous design
• Dual rail encoding vs. data bundling.
• Level vs. transition encoding.
• Speed-independent vs. delay-insensitive design.

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Dual Rail versus Data Bundling

• In dual rail encoded data, each Boolean is
  implemented as two wires.
• This allows the value and the timing information
  to be communicated for each data bit.
• Bundled data, on the other hand, has one wire for
  each data bit and a separate wire to indicate the
  timing.

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Level versus Transition Sensitive

• Level sensitive circuits typically represent a
  logic one by a high voltage and a logic zero by a
  low voltage.
• Transition signaling uses a change in the signal
  level to convey information.

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Speed Independent versus Delay Insensitive

• A speed independent design is tolerant to
  variations in gate speeds but not to propagation
  delays in wires.
• A delay insensitive circuit is tolerant to
  variations in wire delays as well.

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Micropipelines

• Micropipelines were proposed by Michael
  Sutherland in the 1980s.
• Uses separate wires to indicate requests and
  acknowledgements for data.
• Data carried on a bundled bus.

Sutherland I E, "Micropipelines", Communications
of the ACM, vol 32, no 6, June 1989, pp 720-738.
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Micropipelines

• The timing of a micropipeline is as give here
• Note that request and ack are transition
  sensitive.

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Micropipeline Steps

• Sender prepares data
• Sender issues Request
• Receiver accepts data
• Receiver issues Acknowledge
• Sender may remove data at will.
• A micropipeline architecture can be constructed
  using standard CMOS circuits. We saw similar
  functionality in our handshaking adder.

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Null Convention Logic

• Null Convention Logic (NCL) is a logic library
  that can be used to construct delay insensitive
  asynchronous circuits.
• The request and ack signals are merged into the
  data. It forms a symbolically complete logic
  system.
• Introduces a 3rd logic term denoted NULL. This
  indicated that the value is invalid.

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Adding a NULL Element

• Adding a NULL element results in the following
  truth tables for an AND, OR and NOT gate.
• Only when the input(s) are valid can the output
  be valid.

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Three Value Logic

• However now we have 3 value logic (T,F and N).
• Consider the following combinatorial circuit.
• Assume that initially it is in the all NULL state
  and input A becomes valid.

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Data Resolution Wave Front

• When will the outputs (U and V) be non-NULL?
• The can only occur when all their inputs are
  valid. The transition from NULL to non-NULL only
  occurs when the output is valid.
• The transition from NULL to non-NULL propagates
  through the circuit like a wave front.

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Null-Data-Null Cycle

• Note that the transition from NULL to non-NULL
  (Data) indicates the completion of an evaluation
  of valid inputs.
• This is therefore equivalent to an
  acknowledgement signal.
• By setting at least one input to NULL upon an
  acknowledgement we ensure a NULL at the outputs
  sometime later. However not all nets in the
  circuit will become NULL.

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All Null Inputs

• How can we ensure all inputs have been reset to
  NULL?
• Two solutions
• An additional term.
• A feedback element.

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Additional Term

• Add another term to our logic. We denote this
  intermediate. Out truth table becomes
• Now our outputs will only be reset to NULL when
  all inputs are NULL.
• Outputs will therefore cycle through N-gtI-gt(T or
  F)-gtI-gtN.

If timing is exactly balanced then the I states
may not occur.
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Feedback Term

• An alternative is to introduce feedback to NCL
  gates. E.g. AND gate.
• Output can only transition from N to T (or F)
  when inputs are both valid.
• Output can only transition from T (or F) to N
  when both inputs are NULL. This is equivalent to
  Intermediate Signal.

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Feedback Term

• However with the feedback term we must take care.
• If the inputs can change before the feedback term
  is fed-back an error can occur.
• Example What happens when RN, AT and B
  transitions from N-gtT-gtN faster than the
  feedback.
• Therefore the circuit as a whole is no longer
  delay insensitive. However practically we can
  ensure feedback ltlt propagation time.

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NCL Signaling

• So how do we convey these Boolean values in
  digital circuits?
• One method is to use two wires and encode the
  NULL onto both. The complementary value indicates
  DATA. TRUE for one wire and FALSE for the other.
• However what if both wires indicate DATA? Then
  they contradict one another.

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NCL Signaling

• How NCL gets around the problem of two valid
  DATAs is perhaps best illustrated by an example.
  Consider a Half-Adder.

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NCL Half Adder
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Half-Adder Explained

• The NCL gates are majority gates.
• Only one of X_0 and X_1 can be DATA.
• If N or more inputs are not-NULL then output is
  set to DATA.
• E.g. C_1 is only DATA iff A_1 and B_1 are DATA.
  Else it is NULL.

In lower case A_0 and B_0 are DATA.
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HA Behavior
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NULL Completeness

• However the circuit discussed before is not
  complete.
• The outputs can all be NULL even when some of the
  inputs are DATA.
• NCL uses the feedback solution in its majority
  gates.

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NCL Gates with Feedback

• NCL gates use a weighted feedback.
• E.g.
• Also ensure feedback N-1 (N number in box).

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NCL Gate Behavior

• Now NCL gate behaves are follows
• Bold indicates DATA. Output only returns to NULL
  when all inputs are NULL.

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HA Behavior

• Now outputs only return to NULL when all inputs
  are NULL.

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Fault Detection

• By adding one more NCL gate we can detect faults.
• If 3 or 4 outputs are DATA then FAULT is
  asserted.
• FAULT is cleared when all inputs are NULL.

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The Asynchronous Register

• In order to store values we need an asynchronous
  storage element.
• Must acknowledge DATA.
• Must store previous value until new inputs
  settle.

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The Asynchronous Register

• The register can be implemented as a bank of NCL
  gates.
• The four bit register is shown on the right.
• When 4 input wires are VALID an ACK is sent back
  to previous stage.

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Asynchronous Register Pipeline
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Asynchronous Register Pipeline

• Assume circuit begins in all NULL state.
• Both current and next watcher will be requesting
  DATA.
• When four inputs become VALID first watcher
  transitions to NULL.
• VALID data propagates to current register.

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Asynchronous Register Pipeline

• 2nd Watcher then transitions to NULL which
  feedback to previous.
• Forces all previous NCL gates to NULL.

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Another Example

• The registers do not need to be organized in a
  pipeline.
• Here they form a fan-in.
• The right-most register does not trigger an
  acknowledgement until all three inputs are valid.

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NCL in Industry
Source http//www.scism.sbu.ac.uk/ccsv/ACiD-WG/Wo
rkshop2FP5/Programme/FergusonSlides.pdf
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Asynchronous Conclusions

• Offers a non-clocked alternative.
• Potential for
• Lower power.
• Less routing (less area).
• However need to overcome concerns with
  testability and reliability.
• In and out of fashion.