Project by

1
SPARC Architecture

• Project by
• Kirthi Pilla
• Nutan Ladani
• Shobana Sundararajan

2
History

• SPARC architecture dates back to 1987 when it was
  first released. SPARC stems from the RISC
  architecture.Over the years it has grown from a
  CPU architecture to a vehicle for standardized
  UNIX software and has become the foundation upon
  which many manufacturers base new workstation
  products

3
Architecture

• Integer unit architecture (IU)
• Floating point unit architecture (FPU)
• Coprocessor architecture

4
Register Set

• General purpose registers (GPR)
• ---- Integer working registers (r
  registers)
• ---- Floating point registers (f registers)
• Control/status registers (privileged)

5
SPARC Register Model
CWP 1
r31
Ins
r24
r23
locals
CWP
r16
r31
r15
Ins
outs
r24
r8
r23
locals
CWP - 1
r16
r31
r15
Ins
outs
r24
r8
r23
locals
r7
r16
globals
r15
outs
r1
r8
0
r0
6
SPARC Register Windows
7
Instruction Set

• Load and store instructions
• Multiprocessor instructions
• Arithmetic/logical/shift instructions
• Tagged arithmetic instructions
• Floating point computational instructions
• Control transfer instructions
• Coprocessor instructions

8
Processor MicroArchitecture

• Register file unit
• (120 32-bit GPR - 8 global, rest overlapped
  frames of 24 registers each)
• Execution unit
• (32-bit ALU, 32-bit barrel shifter,
  logic/L/S/pipe lining registers )
• Instruction fetch unit
• (processors program counters and
  instruction/data address generation circuitry)
• Control unit
• (instruction pipeline, decoder, processor status
  register, exception/trap handling and interface
  to cache and floating point unit )

9
D
Reg-FILE
Control
ALU
Shift
Addr.gen
AL
Special reg
Result
AH
PCs
F
10
Pipelining

• Four stages
• 1) Fetch 2) Decode 3) Execute 4) Write back

F1
W1
E1
D1
D2
F2
W2
E2
F3
D3
E3
W3
E4
F4
D4
W4
11

LOAD INSTRUCTION
F1
W1
E1
D1
DH1
F2
WH1
EH1
F3
D2
E2
W2
E3

D3
W3
STORE INSTRUCTION
F1
W1
E1
D1
WH1
DH1
F2
EH1
F3
DH2
EH2
WH2
E2

D2
W2

D3
E3
W3
12
Ultra SPARC

• Design Criteria
• The need for a processor that uses multiple
  instructions per cycle led to UltraSPARC.

13
Characteristics

• On chip cache.
• Wide Instruction Fetch.
• Dynamic branch prediction.
• Optimized memory operation in pipeline.
• FP memory access which does not stall FP
  dispatch.
• Write buffer to decouple the processor from store
  completion.
• Ideal for optimized data throughputs.

14
Key Features

• High Performance gt 350SPEC _at_ 167MHz.
• Built using 0.5 micron CMOS process tech.
• Low power operation.
• Static design allows power savings.
• 9 stage pipeline---4 inst. Per cycle.
• Dynamic branch prediction.
• On chip Instruction Data cache,Memory
  Management, Graphics Imaging support.
• Implements new UPA bus architecture.

15
Cache

• Data Cache
• 16KB,direct mapped, virtually indexed
  and tagged. On miss , 16 bytes
• data written into cache from main memory
• Instruction Cache
• 16KB,two way set associative, virtually
  indexed and tagged. On miss ,
• 16 bytes data written into cache from
  main memory.
• External cache
• Size 512K to 4 MB. Handle I D
  misses.Consume 3 cycles.
• Graphics Unit
• 64bit data paths.Provides video
  compression decompression.
• Accelerates graphics by handling
  computations at 10 operations per
• cycle. Uses block load/stores to
  manipulate image.

16
Dynamic Branch Prediction

• Maintains 2-bit prediction for every 2inst. in I
  cache.
• Every branch is predicted.
• Maintains state information for 2,048 branches.
• High efficiency for looping branches.
• Changes predictions for branches only after 2
  mispredictions occur.

17
Branch Following

• Integer Execution Unit
• Memory Management Unit
• Floating Point Unit
• TLB
• 88 of I branches 94 of FP branches are
  successfully predicted.

18
SPARC Compilers
Source program
Front end
Sun IR
Optimizer driver
aliaser
iropt
Sun IR
cgrdr
PCC trees
Code generator
Assembly code
inliner
Assembly code
c2
assembler
relocatable