CPSC 161 Lecture 5

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CPSC 161Lecture 5

• Prof. L.N. Bhuyan
• http//www.cs.ucr.edu/bhuyan/cs161/index.html

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2.9 Instruction Support for Characters

• MIPS (and most other instruction sets) include 2
  instructions to move bytes
• Load byte (lb) loads a byte from memory, placing
  it in rightmost 8 bits of a register
• Store byte (sb) takes a byte from rightmost 8
  bits of register and writes it to memory
• Declare byte variables in C as char
• Assume x, y are declared char, y in memory at
  0(gp) and x at 1(gp). What is MIPS code for x
  y ?
• lb t0,0(gp) Read byte ysb t0,1(gp)
  Write byte x

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What if constant bigger than 16 bits?

• Must keep instructions same size, but immediate
  field (addi) only 16 bits
• Add instruction to load upper 16 bits, then later
  instruction gives lower 16 bits
• load upper immediate (lui) sets the upper 16
  bits of a constant in a register
• Machine language version of lui s0,15
• Contents of s0 after executing lui s0,15

op
rt
rs
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Big Constant Example

• C i 80000 / is1 /
• MIPS Asm
• 80000ten 0000 0000 0000 0001 0011 1000 1000
  0000two
• lui s1, 1 addi s1,s1,14464 0011 1000 1000
  0000
• MIPS Machine Language

s1
0011 1000 1000 0000
0000 0000 0000 0001
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Branch Addressing PC-relative

• Conditional Branch beq t0,t1,label
• address just 16 bits (216), program too small!
• Option always add address to a register PC
  Register Branch address
• Change register contents gt bigger programs
• Which register?
• How use conditional branch? if-else, loops
• Near current instruction gt use PC as reg!
• PC-relative addressing (PC4) /- 215 words

I
6 bits
5 bits
5 bits
16 bits
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Branch Addressing Jumps, J format

• j label go to label
• j has only one operand add format
• large address allows large programs
• bright idea address of instruction always
  multiple of 4 (instructions always words) gt
  store number of word, save 2 bits
• Example j exit exit 10000
• PC address 4 upper 4 bits of old PC

J
6 bits
26 bits
J
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Branch Addressing PC-relative Example

• Loop slt t1,zero,a1 t19,a15
  beq t1,zero,Exit nogtExit
  add t0,t0,a0 t08,a04 subi a1,a1,1
  a15 j Loop goto Loop Exit add
  v0,t0,zero v02,t08

Set t11 if zero lt a1
Address
0
5
9
0
4
9
0
3
8
4
8
0
8
5
5
-1
2
20000
8
0
2
0
8

• Why 20,000?
• Branch address PC address 4 upper 4 bits
  of old PC
• Upper 4 bits of PC for 80016 0000
• Hence new address 20000x4 0000 in upper 4
  bits
• 80,000 0000 0000 0000 0001 0011 1000 1000
  0000two

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MIPS Addressing Modes
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To summarize Need for Test 1
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Alternative Architecture IA - 32

• 1978 The Intel 8086 is announced (16 bit
  architecture)
• 1980 The 8087 floating point coprocessor is
  added
• 1982 The 80286 increases address space to 24
  bits, instructions
• 1985 The 80386 extends to 32 bits, new
  addressing modes
• 1989-1995 The 80486, Pentium, Pentium Pro add a
  few instructions (mostly designed for higher
  performance)
• 1997 57 new MMX instructions are added,
  Pentium II
• 1999 The Pentium III added another 70
  instructions (SSE)
• 2001 Another 144 instructions (SSE2)
• 2003 AMD extends the architecture to increase
  address space to 64 bits, widens all registers
  to 64 bits and other changes (AMD64)
• 2004 Intel capitulates and embraces AMD64
  (calls it EM64T) and adds more media extensions

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IA-32 Overview

• Complexity
• Instructions from 1 to 17 bytes long
• one operand must act as both a source and
  destination
• one operand can come from memory
• complex addressing modes e.g., base or scaled
  index with 8 or 32 bit displacement
• Saving grace
• the most frequently used instructions are not too
  difficult to build
• compilers avoid the portions of the architecture
  that are slow
• what the 80x86 lacks in style is made up in
  quantity, making it beautiful from the right
  perspective

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IA-32 Registers and Data Addressing

• Registers in the 32-bit subset that originated
  with 80386

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IA-32 Typical Instructions

• Four major types of integer instructions
• Data movement including move, push, pop
• Arithmetic and logical (destination register or
  memory)
• Control flow (use of condition codes / flags )
• String instructions, including string move and
  string compare

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IA-32 instruction Formats

• Typical formats (notice the different lengths)

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Summary

• Instruction complexity is only one variable
• lower instruction count vs. higher CPI / lower
  clock rate
• Design Principles
• simplicity favors regularity
• smaller is faster
• good design demands compromise
• make the common case fast
• Instruction set architecture
• a very important abstraction indeed!

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Test 1 on 4/25/06 (Tuesday)

• No conversion to machine code gt No data sheet
  needed. Use Fig. 2.27 instead. However, you still
  have to remember some assembly language
  instructions
• 4 questions with two parts each with varying
  points gt Divide your time accordingly.
• 1 question from general, 1 question from ch 4 and
  2 questions from ch 2.
• Write answers in the space provided, use back
  page if necessary.

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Topics for Test 1

• Lecture slides 1 through 6 available at
  http//www.cs.ucr.edu/bhuyan/cs161/index.html
• Book Chapter 2 (Sections 2.1-2.6, 2.7 pp.
  79-82, 2.9
• Book Chapter 4 (Sections 4.1-4.3)