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Transaction level modeling and SystemC

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Title: Transaction level modeling and SystemC


1
Transaction level modeling and SystemC
2
Agenda
  • SoC
  • TLM
  • SystemC

3
SoC
4
SoC
  • SoC
  • system-on-chip
  • Consists of many components such as processors,
    busses, memories, embedded SW etc.
  • Complete system
  • Can be fit entirely in a single circuit

5
Whats the problem?
  • Increasing complexity of SoC
  • The traditional RTL to layout design and
    verification is inadequate for these systems
  • Shorter time-to-market

6
Solutions
  • TLM
  • Reuse of implementations
  • System standards
  • Extending the flow

7
Levels of abstraction
  • Three levels of abstraction
  • functional level
  • architecture level
  • µArchitecture level

8
TLM
9
Transaction Level Modeling - TLM
  • Transaction - exchange of data or an event
    between two component of a modeled and simulated
    system
  • data can be anything from a word to a complex
    data structure
  • event transaction models synchronization aspects
    that ensure correct operation of the SoC

10
What is TLM?
  • Correspond to the second level of abstraction
    the architecture level
  • Less detailed models than RTL
  • At TLM level we focus only on mapping out data
    flow
  • Type and storing location

11
What is TLM?
  • Can be built as soon as the architectural
    specification is available
  • An abstract level in which
  • The behavior of functional blocks can be
    separated from communication
  • The communication is described in terms of
    sending transactions

12
TLM cont.
  • RTL representation of a SoC platform

TLM representation of a SoC platform
13
TLM for embedded SW (eSW)
  • TLM enables high-speed simulation of developed
    models early in the SoC development lifecycle
  • The speed required for this purpose vary around
    1/1000 to 1/100 of real simulation time of the
    final product
  • A simulation speed of at least 100K transactions
    per second is possible in TLM

14
TLM for embedded SW (eSW)
  • Development takes place in parallel with the RTL
    development

15
TLM for architecture exploration
  • Untimed TLM models provide the first level of
    analysis which is useful for eSW developers
  • Architects are interested in timed TLM

16
TLM for architecture exploration
  • RTL models provide a more precise basis for
    analysis
  • Wrong!
  • Require the effort that goes into TLM development
  • The detailed models are harder to change

17
SoC lifecycle
  • SoC lifecycle will require 3 models one for
    each level of abstraction
  • The functional model can be started at an early
    stage of product specification
  • Once the specification is available work on the
    RTL and TLM begins

18
SoC lifecycle cont.
  • The TLM is built in much shorter time than the
    RTL model
  • eSW and architectural exploration begins with
    first architecture specification
  • After receiving the RTL and the TLM tasks like
    low level SW development and validation can begin

19
SoC lifecycle cont.
  • By the time the first HW emulator board is
    available the eSW is already developed and
    validated

20
SoC lifecycle cont.
  • WATCH OUT!
  • Its important to maintain consistency between
    all levels of abstraction
  • Reusing the same system test vectors
  • Ensuring conformance to expected functionality

21
Design reuse
  • To reduce cost and development time reuse pf
    designs is a must!
  • Reusing design in final stages of implementation
    can end in a different implementation
  • Moving higher in abstraction level can eliminate
    those differences

22
Design reuse
  • This is a first step towards building a library
    of HW and SW implementations at high level
  • Reuse in every shape and form will be necessary
    to cope with increasingly complex embedded systems

23
SystemC
24
SystemC
  • Industry standard language for system design and
    verification
  • Entirely based on C
  • Libraries are easily added as classes

25
SystemC cont.
  • Object oriented design language
  • Defines primary channels for communicating
    transactions

26
SystemC cont.
  • Basic components
  • Module structural entity which contains
    processes, ports, and other modules
  • Channel implements one or more interfaces and
    serves as a container for communication
    functionality
  • Port object through which a module can access a
    channels interface

27
SystemC cont.
  • IMC Interface Method Call
  • Processes calls an interface method of a channel
  • Modules can be connected through their ports to
    the channels

28
SystemC cont.
  • Hierarchical channel contains processes, ports,
    modules and channels

29
Why use SystemC for verification?
  • System level verification is typically done last,
    and is often on the critical path
  • Excellent way to integrate industry norm C/C
    and software models into the verification flow.
  • C is the language of choice for verification
    engineers
  • SystemC excels at transaction level modeling
    (TLM), and TLM is widely used for verification.

30
SystemC Vs. SystemVerilog
  • SystemC
  • Excels in system design and verification
  • Supports TLM, HW/SW co-design, SoC
    architectural analysis and optimization
  • SystemVerilog
  • Excels in HW design and block level verification
  • Retains verilog conciseness and ease to use at
    RTL and gate level
  • Adds many features to support verification

31
SystemC Vs. SystemVerilog
  • SystemC
  • A subset of C/C ideal environment for
    integrating traditional C level tb, easy to
    integrate eSW
  • Reference implementation simulator freely
    available
  • SystemVerilog
  • Adds many features from VHDL that were missing in
    verilog
  • A superset of verilog

32
SystemC Vs. SystemVerilog
33
In one sentence
  • TLM is regarded today as the next step in the
    direction of complex integrated circuits and
    systems design entry
  • automated synthesis tools will increasingly
    support it, allowing design capture to start at a
    higher abstraction level than today

34
THE END!
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