Transaction level modeling and SystemC

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Transaction level modeling and SystemC
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Agenda

• SoC
• TLM
• SystemC

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SoC
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SoC

• SoC
• system-on-chip
• Consists of many components such as processors,
  busses, memories, embedded SW etc.
• Complete system
• Can be fit entirely in a single circuit

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Whats the problem?

• Increasing complexity of SoC
• The traditional RTL to layout design and
  verification is inadequate for these systems
• Shorter time-to-market

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Solutions

• TLM
• Reuse of implementations
• System standards
• Extending the flow

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Levels of abstraction

• Three levels of abstraction
• functional level
• architecture level
• µArchitecture level

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TLM
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Transaction Level Modeling - TLM

• Transaction - exchange of data or an event
  between two component of a modeled and simulated
  system
• data can be anything from a word to a complex
  data structure
• event transaction models synchronization aspects
  that ensure correct operation of the SoC

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What is TLM?

• Correspond to the second level of abstraction
  the architecture level
• Less detailed models than RTL
• At TLM level we focus only on mapping out data
  flow
• Type and storing location

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What is TLM?

• Can be built as soon as the architectural
  specification is available
• An abstract level in which
• The behavior of functional blocks can be
  separated from communication
• The communication is described in terms of
  sending transactions

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TLM cont.

• RTL representation of a SoC platform

TLM representation of a SoC platform
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TLM for embedded SW (eSW)

• TLM enables high-speed simulation of developed
  models early in the SoC development lifecycle
• The speed required for this purpose vary around
  1/1000 to 1/100 of real simulation time of the
  final product
• A simulation speed of at least 100K transactions
  per second is possible in TLM

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TLM for embedded SW (eSW)

• Development takes place in parallel with the RTL
  development

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TLM for architecture exploration

• Untimed TLM models provide the first level of
  analysis which is useful for eSW developers
• Architects are interested in timed TLM

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TLM for architecture exploration

• RTL models provide a more precise basis for
  analysis
• Wrong!
• Require the effort that goes into TLM development
• The detailed models are harder to change

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SoC lifecycle

• SoC lifecycle will require 3 models one for
  each level of abstraction
• The functional model can be started at an early
  stage of product specification
• Once the specification is available work on the
  RTL and TLM begins

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SoC lifecycle cont.

• The TLM is built in much shorter time than the
  RTL model
• eSW and architectural exploration begins with
  first architecture specification
• After receiving the RTL and the TLM tasks like
  low level SW development and validation can begin

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SoC lifecycle cont.

• By the time the first HW emulator board is
  available the eSW is already developed and
  validated

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SoC lifecycle cont.

• WATCH OUT!
• Its important to maintain consistency between
  all levels of abstraction
• Reusing the same system test vectors
• Ensuring conformance to expected functionality

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Design reuse

• To reduce cost and development time reuse pf
  designs is a must!
• Reusing design in final stages of implementation
  can end in a different implementation
• Moving higher in abstraction level can eliminate
  those differences

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Design reuse

• This is a first step towards building a library
  of HW and SW implementations at high level
• Reuse in every shape and form will be necessary
  to cope with increasingly complex embedded systems

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SystemC
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SystemC

• Industry standard language for system design and
  verification
• Entirely based on C
• Libraries are easily added as classes

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SystemC cont.

• Object oriented design language
• Defines primary channels for communicating
  transactions

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SystemC cont.

• Basic components
• Module structural entity which contains
  processes, ports, and other modules
• Channel implements one or more interfaces and
  serves as a container for communication
  functionality
• Port object through which a module can access a
  channels interface

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SystemC cont.

• IMC Interface Method Call
• Processes calls an interface method of a channel
• Modules can be connected through their ports to
  the channels

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SystemC cont.

• Hierarchical channel contains processes, ports,
  modules and channels

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Why use SystemC for verification?

• System level verification is typically done last,
  and is often on the critical path
• Excellent way to integrate industry norm C/C
  and software models into the verification flow.
• C is the language of choice for verification
  engineers
• SystemC excels at transaction level modeling
  (TLM), and TLM is widely used for verification.

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SystemC Vs. SystemVerilog

• SystemC
• Excels in system design and verification
• Supports TLM, HW/SW co-design, SoC
  architectural analysis and optimization

• SystemVerilog
• Excels in HW design and block level verification
• Retains verilog conciseness and ease to use at
  RTL and gate level
• Adds many features to support verification

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SystemC Vs. SystemVerilog

• SystemC
• A subset of C/C ideal environment for
  integrating traditional C level tb, easy to
  integrate eSW
• Reference implementation simulator freely
  available

• SystemVerilog
• Adds many features from VHDL that were missing in
  verilog
• A superset of verilog

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SystemC Vs. SystemVerilog
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In one sentence

• TLM is regarded today as the next step in the
  direction of complex integrated circuits and
  systems design entry
• automated synthesis tools will increasingly
  support it, allowing design capture to start at a
  higher abstraction level than today

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THE END!