Observe due measure, for right timing is in all things the most important factor'

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• Observe due measure, for right timing is in all
  things the most important factor.
• Hesiod (800 BC), Works and Days

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CSE 502NFundamentals of Computer Science

• Fall 2004
• Lecture 23
• Gate Delays
• Storage elements
• Synchronous Circuit Timing

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Integrated Circuits

• Digital logic is implemented using transistors in
  integrated circuits containing many gates.
• small-scale integrated circuits (SSI) contain 10
  gates or less
• medium-scale integrated circuits (MSI) contain
  10-100 gates
• large-scale integrated circuits (LSI) contain up
  to 104 gates
• very large-scale integrated circuits (VLSI)
  contain gt104 gates
• Improvements in manufacturing lead to ever
  smaller transistors allowing more per chip.
• gt107 gates/chip now possible doubles every 18-24
  months
• Variety of logic families.
• TTL - transistor-transistor logic
• CMOS - complementary metal-oxide semiconductor
• ECL - emitter-coupled logic
• GaAs - gallium arsenide

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CMOS Logic Gates

• CMOS integrated circuits are built using two
  types of Field Effect Transistors (FET), n-type
  p-type.

• the gate (note different meaning) input controls
  whether current can flow between the other two
  terminals or not.

• Logic gates are constructed by combining
  transistors in complementary arrangements.

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Circuit Delays in CMOS Circuits

• Electronic gates are physical devicesthat take
  time to operate.

• Response to instantaneous change atX is gradual
  decrease in voltage atY and similar gradual
  increase at Z.
• Voltage at Y must drop below logicthreshold
  level to be seen as a 0.
• This effect can be viewed as delay in propagation
  of logic values.
• tPLH denotes low-to-high delay
• tPHL denotes high-to-low delay
• tpd maxtPLH, tPHL
• relative values of tPLH and tPHL depend on
  relative strength of pull-up and pull-down
  transistors in inverters
• values vary with operating temperature and
  manufacturing processes

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Closer Look at CMOS Circuit Delays

• When X goes high, pull-up of first inverter turns
  off and pull-down turns on.

• Decrease of voltage at Y requires transfer of
  charge from capacitor to ground.
• wires and transistor gates act like capacitors
• time for transfer depends on size of capacitance
  and on resistance of pull-down transistor
• pull-up pull-down transistors can have
  different on-state resistance values
• Use of two parallel inverters between X and Y can
  give faster logic transitions.

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Program Counter Schematic (4 bit)
flip flop
inputmux
incrementlogic
resetlogic
tri-statebuffer
same inputs,different outputs
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Program Counter in VHDL

• entity program_counter is
• port (
• clk, en_A, ld, inc, reset in STD_LOGIC
• aBus out STD_LOGIC_VECTOR(15 downto 0)
• dBus in STD_LOGIC_VECTOR(15 downto 0)
• )
• end program_counter
• architecture pcArch of program_counter is
• signal pcReg STD_LOGIC_VECTOR(15 downto 0)
• begin
• process(clk) begin
• if clk'event and clk '1' then
• if reset '1' then pcReg lt x"0000"
• elsif ld '1' then pcReg lt dBus
• elsif inc '1' then
• pcReg lt pcReg x0001"
• end if
• end if
• end process

PCregister
resetlogic
outputto aBus
incrementlogic
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VHDL PC Simulation
increment
load
load
enable output
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Clocked Sequential Circuits

• In sequential circuits, output values may depend
  on both current and past input values.
• consists of combinational circuit and set of
  storage elements
• each storage element stores one bit of
  information
• the state of a sequential circuit is the set of
  stored values
• In clocked sequential circuits, state changes are
  driven by clock signals.
• information stored using flip-flops.

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Edge-Triggered D Flip Flop

• D flip flop stores value at D input when clock
  rises.
• Most widely used storage element for sequential
  circuits.
• Propagation time is time from rising clock to
  output change.
• If input changes when clock rises, new value is
  uncertain.
• output may oscillate or may remain at
  intermediate voltage (metastability)

• Timing rules to avoid metastability
• D input must be stable for setup time before
  rising clock edge
• must remain stable for hold time following rising
  clock edge

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Serial Parity Generator

• Circuit with data input, enable input parity
  output.
• output is high if number of 1s in input bit
  stream is odd

• Next state table gives next state and output, as
  function of current state and input.

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Input Timing for Parity Circuit

• To meet setup hold time requirements of flip
  flop, inputs to circuit must be stable during
  certain times.
• let setup time2 ns, hold time1 ns and gate
  delay1 ns
• then D must be stable from 4 ns before clock edge
  until 1 ns before clock edge similarly for EN
• these input conditions are summarized in timing
  diagram
• if gate delay can vary between .4 and 1.5 ns,
  then stable period for D is from 5 ns before
  clock edge to .2 ns after.

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The SR Latch

• Pair of inverters provides stable storage.
• To enable stored value to be changed, use
  cross-coupled NOR gates.
• equivalent to inverter pair when both inputs are
  low
• SR latch is key building block for flip flops.
• when S1, R0 latch is set
• when S0, R1 latch is reset
• when S0, R0 latch retains value
• when S1, R1 latch state is undefined

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S-R Latch Behavior
metastability

• Note that when SR1, both outputs are low.
• outputs are not complements of each other in this
  case
• When S, R drop together, the latch output is
  undefined.
• may remain at intermediate voltage
• or, may oscillate between low and high values
• Latch metastability can lead to unpredictable
  circuit behavior.
• For these reasons, the SR1 condition should be
  avoided.

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More on SR Latches
SR Latch with Control Input

• SR latch most often implemented with NAND gates.
• inputs are active low (negative logic inputs)
• when both inputs are low, both outputs high
• when inputs rise together, outputs can become
  metastable

• SR latch with control input changes state only
  when control input is high.
• inputs are active high
• forbidden input condition is CSR1
• change S, R inputs when C0

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D Latch

• The D latch stores the value on the D input when
  the enable input is asserted.
• no forbidden input combinations
• but input should be stable when the control input
  drops
• if not, outputs may become metastable

• Alternative implementation uses transmission
  gates.
• TGs enable either input or feedback path
• in CMOS, this uses 10 transistors vs. 18

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Implementing D Flip Flops

• When clock rises, value in D-latch propagates to
  SR-latch and outputs.
• New value determined by D input at time clock
  rises.
• Flip flop setup and hold time conditions designed
  to prevent metastability in latches.
• Propagation delay determined primarily by
  SR-latch delay.

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SR Master-Slave Flip Flop

• The SR master-slave flip flop uses two SR latches
  with complementary enables.

• First stage follows all changes while clock is
  high, but second stage only sees value after
  the clock drops.
• not the same as a negative edge-triggered flip
  flop
• Forbidden input combination causes metastability.
• Recommended usage change S, R only when C0.

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Types of Latches and Flip Flops
Standard Graphic Symbols
Characteristic Tables
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Synchronous Circuits

• Synchronous circuits typically employ
  edge-triggered flip-flops and operate on a global
  clock
• Clock is distributed to all flip-flops in the
  circuit
• Large circuit designers must worry about
  capacitive loading, jitter, etc.
• Maximum clock frequency is determined by critical
  path in the design
• The critical path in the design is the path from
  the output of a flip-flop to the input of a
  flip-flop with the maximum gate delay

logic
A
logic
x
B
y
logic
logic
C
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Synchronous Circuit Timing

• Must guarantee that flip-flop setup and hold
  times are not violated
• Often want to find the maximum clock frequency
  for synchronous circuit
• Compute maximum critical path delay
  max(td)Tminclk max(tCQ) max(td) tsetup
  Fmaxclk 1/ Tminclk
• Check for hold time violation min(tCQ) min(td)
  gt thold
• Example tXOR (1.5ns 2ns), tAND tOR
  (0.8ns 1.2ns)tCQ (0.5ns 1ns), tsetup
  2ns, thold 1.5ns

clk