Processor Design

1
Processor Design

• Computer ArchitectureCS 215

2
Registers

• Special purpose registers
• Accumulators (arithmetic registers)
• Status register

3
Machine Types

• Accumulator machines
• Limited number of data accumulators
• 1-address machines
• Stack machines
• No register names
• Registers organized as a stack
• 0-address machine
• General register machines
• Most often used today
• Registers used for almost any purpose

4
Instruction Sets

• Each family of CPUs has its own instruction set
• Instruction codes are mapped to instructions
• Data movement
• Arithmetic
• Logic
• Control

5
Instructions

• Must contain
• Which operation to perform
• Where to find the operand(s), if any
• Where to put the result, if any
• Where to find the next instruction

6
Memory Access

• Each register has a unique address
• Two operations
• Read
• Write

7
Memory Access Read

• CPU places an address on the address bus, and a
  read request on the control bus
• Memory unit receives request, decodes address,
  and locate data at address
• Memory unit places data on data bus
• Memory unit places a complete message on control
  bus

8
Memory Access Write

• CPU places an address on the address bus, value
  to be written on data bus, and a write request on
  the control bus
• Memory unit receives request, decodes address
• Memory unit stores data at address
• Memory unit places a complete message on control
  bus

9
Addressing Modes

• Immediate
• i
• Direct
• Mi
• Indirect
• MMi

• Register direct
• Ri
• Register indirect
• MRi
• Displacement
• MRic
• Relative
• MPCc

10
SRC Instructions

• Load instructions
• ld, ldr, la, lar
• Store instructions
• st, str
• Arithmetic
• add, addi, sub, neg

• Logic
• and, andi, or, ori, not
• shr, sha, shl, shc
• Branching
• br, brl
• Miscellaneous
• nop, stop

11
Instruction Formats
ld, st, la, addi, andi, ori
31 27 26 22 21 17 16 12 11 4 2 0
Op
ra
rb
c2
ldr, str, lar
31 27 26 22 21 17 16 12 11 4 2 0
Op
ra
c1
12
Instruction Formats
neg, not
31 27 26 22 21 17 16 12 11 4 2 0
Op
ra
unused
unused
rc
br
31 27 26 22 21 17 16 12 11 4 2 0
Op
unused
(c3) unused
rb
rc
Cond
13
Instruction Formats
brl
31 27 26 22 21 17 16 12 11 4 2 0
Op
ra
(c3) unused
rb
rc
Cond
add, sub, and, or
31 27 26 22 21 17 16 12 11 4 2 0
Op
ra
unused
rb
rc
14
Instruction Formats
shr, shra, shl, shc
31 27 26 22 21 17 16 12 11 4 2 0
Op
ra
(c2) unused
rb
Count
31 27 26 22 21 17 16 12 11 4 2 0
Op
ra
(c3) unused
rb
rc
00000
nop, stop
31 27 26 22 21 17 16 12 11 4 2 0
Op
unused
15
Example

• cnt .equ 8
• .org 0
• seq .dc 1
• next .dc 1
• ans .dw cnt
• .org 0x1000
• lar r31, loop
• la r0, cnt
• la r1, seq
• loop ld r2, seq(r1)
• ld r3, next(r1)
• add r2, r2, r3
• st r2, ans(r1)
• addi r1, r1, 4
• addi r0, r0 -1
• brnz r31, r0
• stop

16
CPU Design
CPU
Control Unit

• Control Unit
• Generates the control signals in the correct
  order to effect the correct data path activity
• Data Path
• Set of interconnections and auxiliary registers
• Needed to accomplish overall changes an
  instruction makes

Control signals out
Control unit inputs
Data Path
17
Register Transfer Notation
18
1-Bus Microarchitecture

• Only one value can be placed on the bus at any
  time

19
Abstract Vs. Concrete RTN

• How would accomplish the following instruction
  using this architecture?
• add(op12)?Rra?RrbRrc

20
Abstract Vs. Concrete RTN

• add(op12)?Rra?RrbRrc
• Step RTN

21
Abstract Vs. Concrete RTNaddi

• Step RTN
• T0. MA ? PC C ? PC 4
• T1. MD ? MMA PC ? C
• T2. IR ? MD
• T3. A ? Rrb
• T4. C ? A c2lt16..0gt sign ext.
• T5. Rra ? C

22
Abstract Vs. Concrete RTNld

• Step RTN
• T0-T2 Instruction fetch
• T3. A ? (rb0 ? 0 rb?0 ? Rrb)
• T4. C ? A (16_at_IRlt16gtIRlt15..0gt)
• T5. MA ? C
• T6. MD ? MMA
• T7. Rra ? MD

23
Abstract Vs. Concrete RTNst

• Step RTN
• T0-T2 Instruction fetch
• T3. A ? (rb0 ? 0 rb?0 ? Rrb)
• T4. C ? A (16_at_IRlt16gtIRlt15..0gt)
• T5. MA ? C
• T6. MD ? Rra
• T7. MMA ? MD

24
Abstract Vs. Concrete RTNbr

• Step RTN
• T0-T2 Instruction fetch
• T3. CON ? cond(Rrc)
• T4. CON ? PC ? Rrb

25
Abstract Vs. Concrete RTNshr

• Step Concrete RTN
• T0-T2 Instruction fetch
• T3. n ? IRlt4..0gt
• T4. (n0) ? (n ? Rrclt4..0gt?
• T5. C ? Rrb
• T6. Shr ( (n?0)?(Clt31..0gt?0Clt31..1gt?n ? n-1
  Shr) )
• T7. Rra ? C

26
More Detail
27
More Detail
ra, rb, rc fields
28
Try this!

• Problem
• Extend the SRC instruction set by adding the XOR
  command (op19), similar to the AND commandNote
  The ALU cannot be altered by adding XOR
• Develop both an abstract and concrete RTN for the
  instruction

29
Try this!
30
Instruction Register
31
Memory Interface
From bus
From memory
To memory
To bus
32
ALU
33
ALU
34
Control sequencesInstruction Fetch

• Step Concrete RTN Control Sequence
• T0. MA ? PC C ? PC4 PCout, MAin, Inc4, Cin
• T1. MD ? MMA PC ? C Read, Cout, PCin, Wait
• T2. IR ? MD MDout, IRin
• T3. Instruction_execution

35
Control sequencesadd
Step Concrete RTN Control Sequence T0. MA ? PC
C ? PC4 PCout, MAin, Inc4, Cin, Read T1. MD ?
MMA PC ? C Cout, PCin, Wait T2. IR ?
MD MDout, IRin T3. A ? Rrb Grb, Rout,
Ain T4. C ? A Rrc Grc, Rout, ADD,
Cin T5. Rra ? C Cout, Gra, Rin, End
36
Control sequencesaddi
Step Concrete RTN Control Sequence T0. MA ?
PC C ? PC 4 PCout, MAin, Inc4, Cin T1. MD ?
MMA PC ? C Cout, PCin, Wait, Read T2. IR ?
MD MDout, IRin T3. A ? Rrb Grb, Rout,
Ain T4. C ? A c2?16..0? sign ext. c2out,
ADD, Cin T5. Rra ? C Cout, Gra, Rin, End
37
Control sequencesst
38
Control sequencesshr
Step Concrete RTN Control Sequence T0-T2 Instruc
tion fetch Instruction fetch T3. n ?
IR?4..0? c1out, Ld T4. (n0) ? (n ?
Rrc?4..0?) n0 ? (Grc, Rout, Ld) T5. C ?
Rrb Grb, Rout, CB, Cin T6. Shr
((n?0)? n?0 ? (Cout, SHR, Cin, (C?31..0? ?
0C?31..1? Decr, Goto6) n ? n-1 Shr)
) T7. Rra ? C Cout, Gra, Rin, End
39
Control sequencesbr
Step Concrete RTN Control Sequence T0-T2 Instruct
ion fetch Instruction fetch T3. CON ?
cond(Rrc) Grc, Rout, CONin T4. CON ? PC ?
Rrb Grb, Rout, CON ? PCin, End
40
Clocking Timing
41
Control Unit
42
2-Bus SRC
43
3-Bus SRC
44
Machine Reset

• From a need to initialize processor to a known,
  defined state
• Control Step Counter ? 0
• PC ? Known Value

• RTN
• instruction_interpretation (?Run?Strt ? (Run
  ? 1 PC, R0..31 ? 0)
• Run??Rst (IR ? MPC PC ? PC
  4instruction_execution)
• Run?Rst ? ( Rst ? 0 PC ? 0) instruction_interpre
  tation)

45
Types of Exceptions

• System Reset
• Machine Check Exceptions
• Memory error checking
• Data Access Exceptions
• Instruction Access Exceptions
• Alignment Exceptions

46
Types of Exceptions

• Program Exceptions
• Illegal instruction
• Unimplemented instruction
• Privileged instruction
• Arithmetic errors (sometimes)

47
Types of Exceptions

• Miscellaneous Hardware Exceptions
• Countdown to zero
• Trace Debugging Exceptions
• Nonmaskable Exceptions
• Cannot be ignored
• Power outage
• Interrupts (External)

48
Exception Process

• Interrupt signal asserted
• Determine if interrupt should be serviced Finish
  current instruction, if possible

49
Exception Process
instruction_interpretation (?Run?Strt ? Run
? 1 Run??(ireq?IE) ? (IR?? MPC PC ? PC 4
instruction_execution) Run?(ireq?IE) ? (IPC ?
PC?31..0? II?15..0? ??Isrc_info?15..0? iack
??1 IE ??0 PC ? Ivect?31..0? iack ? 0)
instruction_interpretation)