Datapath and Control (Multicycle datapath)

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Datapath and Control(Multicycle datapath)
CDA 3101 Discussion Section 11
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Question 1

• Show any necessary modifications in the
  multicycle datapath and control figures given on
  the next slides to support the following
  instruction.
• addm rd, rs, rt rd rs Memrt
• This instruction is an R-format instruction. Make
  sure it does not break the other instructions
  (like add, sub, and, or, beq, lw, sw, j) which
  are supported by the datapath and control.

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Question 1
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Question 1
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Question 1
We use the same datapath, but there are a few
highly significant changes which must be
made. 1. Instruction fetch same 2. Instruction
decode - We will have to look at the funct field
to determine that this instruction is addm. 3.
Execution - We have to get the second operand
from memory before activating the ALU. 4.
Instruction completion RegIR15-11 ALUOut.
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Question 2

• Consider the multi-cycle datapath in Fig. 5.28
  and the FSM in Fig. 5.38 of the textbook. Say the
  datapath is executing the following instruction
  sequence
• loop  add t0,t0,t1
• lw t3, 0(t5)
• beq t3,t4,loop
• Assume the program counter is initially set to
  the add instruction and the add instruction
  is fetched in clock cycle 1. The add instruction
  will take 4 cycles, lw will take 5 cycles and beq
  will take 3 cycles to execute.
• Number these cycles 1, 2, 3, 4, 5, .,12.

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Question 2 (more)

• For each of these 12 cycles , provide the values
  for the various registers contents and the
  values of the control signals (listed below) that
  would exist in the circuit after all the work
  for that cycle has completed, right before the
  moment the rising edge of the next clock cycle
  occurs.
• Provide justification for each value you write.
  You can put X for a register value that can not
  be determined from the information provided.

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Question 2 (more)

• Provide exact values in binary or hex even if
  that value is not used in the instruction being
  executed. For example, for add instruction the
  branch target address will not be used, but it
  will be computed in cycle 2 in such a case,
  compute the branch target address and provide the
  value. To be able to do this, you need to find
  the binary representation of each instruction (in
  the above instruction sequence).
• Assume t0 0x00000001, t1 0x00000002, t4
  0x00000004, t50x10008000, the contents at
  memory location 0(t5) is 0x00000005, the address
  of the first instruction is 0x00400040.

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Question 2 (Format)

• PC
• IR (Instruction Register)
• MDR (Memory Data Reg.)
• A
• B
• ALUOut
• t0
• t3

• ALUSrcA
• ALUSrcB
• ALUOp
• 4-bit output of ALU Cntl
• PCSource
• Zero