Pentium Logic Symbol

1
Pentium Logic Symbol
2
Pentium Pins (Dual Mode)
3
Pentium In Circuit

• D/C, M/IO, W/R encode the bus cycle identifier
  in place of MEMR etc
• External system has to generate WE, OE, RAS,
  CAS etc
• Pentium Bus optimised for fast cache line fills
• 64b data bus improves data transfer rate

4
Pentium byte addressing using 64-bit data bus
This is similar to the way that the 8086 used
BHE and BLE/A0 to select bytes from a 16-bit bus
5
Data Alignment

• Pentium can access D63-D0 per transfer cycle
• Arrange objects (bytes, words, double words, quad
  words) so that they can be accessed in one
  transfer cycle

with Address xxxx xxxx xxxx xxxx xxxx xxxx xxxx
x000b
6
Data Alignment

• Pentium Aligment Rules
• No need to align 1-byte data (char, byte)
• Align 2-byte data so that it doesnt cross a
  4-byte boundary (int)
• Align 4-byte data on 4-byte boundaries(double
  word)
• Align 8-byte data on 8-byte boundaries(MMX data
  types)

7
Single Transfer Cycle (No Wait)
8
Single Transfer Cycle Wait State
9
Burst Transfer Cycles

• Used for cache line fills and write-backs
• Burst Mode New data can be sampled or driven in
  consecutive clocks
• 64b data bus 8B per (single transfer)
• Burst cycle transfers 32B in four cycles
• Data contiguous and aligned to 32B boundaries
• Corresponds to internal Pentium cache line
• With no waits can transfer 32B in 5 clock cycles
• 2-1-1-1 burst

10
Data Alignment

• Block of 32 bytes can be transferred in one burst
  cycle
• Aligned to 32-byte boundaries

with Address xxxx xxxx xxxx xxxx xxxx xxxx xxx0
0000b
11
Burst Read Cycles
12
Burst Mode Address Cycling
13
Burst Write Cycles
Burst Writes always follow a fixed
sequence 00h-08h-10h-18h
14
Address Pipelining (1)

• Uses the NA signal to tell memory controller to
  start decoding the next address even though the
  last data transfer has not yet been completed
• Counts the number of BRDY signals returned so it
  knows which burst is going on

15
Address Pipelining (2)
16
Special Cycles

• D/CM/IO0 and W/R1 indicate that a special
  cycle is in progress
• BE7-BE0 identify the type of special cycle

17
Inquiry (Snoop) Cycles

• Multiprocessors use inquiry cycles to implement
  the MESI protocol
• External unit can check if data at a specific
  address is in the on-chip cache of the Pentium
• External unit can invalidate the stored data and
  the corresponding cache line.

18
Inquiry cycle invalidating a non-modified line
19
System Management Mode(SMM)

• Important because of high power dissipation of
  Pentium
• Two signals for SMM
• SMI (input) and SMIACT (output)
• Pentium can only leave SMM after and RSM
  instruction has been executed
• The SMI is implemented as an interrupt
• SMM operates in extended Real Mode like Real
  Mode but with 32-bit offset registers

20
SMM SRAM

• SMM use battery-backed up SRAM at 30000h to
  3FFFFh
• Normally overlays some DRAM addresses
• If SRAM used, must disable DRAM in SMM and the
  must disable SRAM after exiting SMM
• SMIACT can be used for this purpose

21
Dual Processing support
22
Dual Processing Bus Arbitration

• One Pentium is Most Recent Master (MRM)
• Other is Least Recent Master (LRM)
• If the LRM wants the bus
• LRM asserts PBREQ
• MRM completes any pending bus cycles and grants
  the bus
• MRM asserts PBGNT 
• LRM becomes the new MRM
• New MRM controls the signals to the common
  L2-cache, main memory and I/O 
• The rest of the system sees only one Pentium

23
Atomic (Indivisible) Accesses

• Some accesses to main memory must not be
  interrupted
• The LOCK signal tells the system that subsequent
  memory accesses are atomic
• PBREQ cannot block atomic sequences
• LOCK signal is output due to
• The LOCK prefix on some instructions
• Interrupt acknowledge cycles
• Segment descriptor, page directory and page table
  updates
• The XCHG instruction
• LOCK signal on its own does not lock current
  memory accesses external hardware has to use the
  LOCK signal to lock memory accesses

24
Cache Consistency

• If memory accessed by the MRM is in the LRMs
  cache, the LRM asserts PHIT
• MRM changes the corresponding line in its cache
  to S (shared)
• If a hit occurs in the MRM onto a modified cache
  line the LRM (Processor B) asserts PHIT and the
  MRM (Processor A) does a back-off sequence
• Processor A (MRM) completes the current bus cycle
  but ignores the data from the system
• Processor A gives control to Processor B (LRM), B
  becomes new MRM
• Processor B, new MRM, writes back the cache line
  into the L2-cache or the main memory
• Processor B (new MRM) gives control back to
  Processor A (original MRM). Processor A carries
  out the original bus cycles using the data it got
  from the LRM.

25
APIC for Dual Processing