How to Detect Redundancy

1
How to Detect Redundancy
(500, 50) (400, 40) (300, 35) (250, 30) (300,
40) (300, 30) (300, 25) (250, 20)
(500, 50) (400, 40) (300, 35) (300, 40) (300,
30) (300, 25) (250, 20) (250, 30)
1. Sort according to slack Q 2. Scan in
decreasing order of Q 3. Delete if C is not
decreasing
2
More on Gate Sizing

• If we increase the gate width
• Driving resistance decreases, therefore the time
  to charge and discharge downstream load decreases
• Input capacitance increases, therefore the time
  to charge and discharge for the previous stage
  increases
• Need to consider overall tradeoff

3
Wire Sizing

• The metal wire can also be sized
• The wider the wire, the less the resistance, the
  greater the capacitance

Cell
Cell
4
Power Dissipation of CMOS

• Static dissipation
• Sub-threshold leakage from source to drain
• Reverse bias leakage from diffusion to substrate
• Gate leakage from gate to drain

5
Leakage Power

• Static power
• Ps(supply voltage)(leakage current)
• As the technology shrinks feature size, static
  power increases dramatically
• Gate length decreases
• Gate oxide thickness decreases
• Gate count increases
• Leakage current increases

6
Dynamic Power

• Charging and discharging Cload
• PdCload (Vdd)2 f Psc
• where f is frequency of signal switching

Cload
7
Dynamic Power II

• Short circuit current Isc
• Psc2fImeanVdd

vdd-vtn
vtn
8
Power Minimization

• Transistor sizing
• Smaller the transistor, less the dynamic and
  static power
• Interconnect optimization
• Make wire shorter and thinner, thereby reducing
  Cload
• Reduce power supply voltage, but this also slows
  down the circuit
• Use dual supply voltage Vhigh and Vlow, Vhigh for
  time critical paths, and Vlow for other paths

9
Power Optimization

• Increase threshold voltage to reduce leakage, but
  this also increases delay
• Dual threshold voltage, low threshold for time
  critical paths, high threshold for other paths
• More advanced techniques
• Logic synthesis to reduce switching activity
• Sleep state, power gating, clock gating, glitch
  reduction,

10
Power and Ground

• As the chip size increases, IR drop due to sudden
  current change causes noise and error
• Coordinated dynamic power usage may cause Vdd
  charge in a region
• If Vdd changes, delay may increase or decrease

11
Power/Ground Analysis

• Solve a differential equation of RCL circuit to
  see if any part has power starvation
• Gx(t) Cx(t) h(t)