Digital Integrated Circuits A Design Perspective

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Digital Integrated CircuitsA Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
The Inverter
March 9, 2004
2
Current Schedule
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Proposed Modification
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Class Information

• Hw. 2 extended to Wed. 3/10. On 3/12 we will
  distribute copy of our solution.
• Lectures on 3/16 and 3/18 Garcia
• Midterm 1 moved to 3/13. Covers material up to
  Hw.3 and Ch. 5.
• Midterm 2 moved to 4/21. Covers material up to
  P.2 and Ch. 7.

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Power Dissipation
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Where Does Power Go in CMOS?
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Dynamic Power Dissipation
2
Energy/transition C
V
L
dd
2
Power Energy/transition
f
C
V

f
L
dd
Not a function of transistor sizes!
Need to reduce C
, V
, and
f
to reduce power.
L
dd
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Modification for Circuits with Reduced Swing
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Adiabatic Charging
2
2
2
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Adiabatic Charging
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Node Transition Activity and Power
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Transistor Sizing for Minimum Energy

• Goal Minimize Energy of whole circuit
• Design parameters f and VDD
• tp ? tpref of circuit with f1 and VDD Vref

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Transistor Sizing (2)

• Performance Constraint (g1)
• Energy for single Transition

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Transistor Sizing (3)
VDDf(f)
E/Ereff(f)
F1
2
5
10
20
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Short Circuit Currents
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How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall gtgt
trise, but cant do this for cascade logic, so ...
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Minimizing Short-Circuit Power
Vdd 3.3
Vdd 2.5
Vdd 1.5
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Leakage
Sub-threshold current one of most compelling
issues in low-energy circuit design!
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Reverse-Biased Diode Leakage
JS 10-100 pA/mm2 at 25 deg C for 0.25mm
CMOS JS doubles for every 9 deg C!
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Subthreshold Leakage Component
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Static Power Consumption
Wasted energy Should be avoided in almost all
cases, but could help reducing energy in others
(e.g. sense amps)
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Principles for Power Reduction

• Prime choice Reduce voltage!
• Recent years have seen an acceleration in supply
  voltage reduction
• Design at very low voltages still open question
  (0.6 0.9 V by 2010!)
• Reduce switching activity
• Reduce physical capacitance
• Device Sizing for F20
• fopt(energy)3.53, fopt(performance)4.47