Pixel Hit Merging, Grouping etc.

1
Pixel Hit Merging, Grouping etc.

• Jan. 2005

2
Outline

• Grouping adjacent hits in same column saves data
  volume by factor of 1.5-2, as good as BCO
  ordering.
• Hit grouping needs no FIFO, it is a lot simpler
  than BCO ordering.
• Reduced data volume requires smaller buffer while
  doing BCO ordering and one-turn-per-highway
  scheme.
• Keep an eye open on instantaneous rate
• BCO ordering will increase instantaneous rate to
  L1 trigger.
• Hit grouping will not.
• Merging 72 channels together in PDCB needs some
  thought.

3
Input of PDCB
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
b20
b19
b18
b17
b16
b23
b22
b21
Hit24
Row
Column
BCO(70)
ADC
1
DCC et al
Added in PDCB
Module
Chip
Turn (Expanded BCO)
4
Input to L1 Trigger (Pack 4 ADC Using 13 bits)
Idle
1
1
1
1
0
00
7
BCO Word
BCO(70)
1
1
1
0
0
0
Tn(10)
Column Word
Row
Column
Module
ADC Word
ADC3
Chip
ADC0
ADC1
ADC2
Hits
Status, Stn, hp. headers
Status etc.
1
1
1
1
0
0-6
Timing related info/headers
Timing Info etc.
1
1
1
0
0
1
0-3
Column
0
0
X
X
X
Invalid Column coding
1
1
1
X
0
5
TSO Module Receiving Data from PDCB
Buff
PTSM FPGA
VME P1
Buff
Buff
Optical Receiver
P2
Inputs from 3 PDCBs
To be merged to 32-bit RAM
6
Merging in TSO FPGA
ADC Word C2
ADC Word B2
ADC Word A2
Column Word C2
Column Word B2
Column Word A2
BCO Word C2
BCO Word B2
BCO Word A2
3 Clock (125 MHz) cycles
ADC Word C1
ADC Word B1
ADC Word A1
Column Word C1
Column Word B1
Column Word A1
BCO Word C1
BCO Word B1
BCO Word A1
BCO Word C2
ADC Word C2
Column Word C2
BCO Word B2
ADC Word B2
Column Word B2
BCO Word A2
ADC Word A2
Column Word A2
BCO Word C1
ADC Word C1
Column Word C1
3 Clock (125 MHz) cycles
BCO Word B1
ADC Word B1
Column Word B1
BCO Word A1
ADC Word A1
Column Word A1
Address to RAM
Data (32-bit) to RAM
7
How to Pack 4 ADC Using 13 bits

• There are 9 states for a sensor not hit or ADC
  0-7.
• 4 ADCs can not be packed in 12 bits, can be
  packed in 14 bits (4x3 2 bits of hits), but
  we have only 13 bits.
• In theory, 13 bits can pack 4 items with 10
  states each. So 4 ADC with 9 states each can be
  packed simply.
• There are several ways to pack the 4 hits.

ADC3
Chip
ADC0
ADC1
ADC2
Hits
ADC3
Chip
1
ADC0
ADC1
ADC2
Chip
0
ADC0
ADC1
ADC2
1
1
0
Chip
ADC0
ADC1
0
1
Chip
ADC0
0
0
1
ADC3
Chip
ADC0
ADC1
ADC2
M3
M2
M1
M0
ADC3
Chip
1
ADC0
ADC1
ADC2
Chip
0
ADC0
ADC1
ADC2
1
1
1
0
Chip
ADC0
ADC1
0
1
1
1
Chip
ADC0
0
0
0
8
Pixel Hit Grouping
Module
Row1
Column1
BCO1
ADC0
1
Chip
Module
Row11
Column1
ADC1
1
BCO1
Chip
Module
Row2
Column2
ADC0
1
BCO2
Chip
Module
Row21
Column2
ADC1
1
BCO2
Chip
Module
Row22
Column2
ADC2
1
BCO2
Chip
Module
Row23
Column2
ADC3
1
BCO2
Chip
Module
Row24
Column2
ADC4
1
BCO2
Chip

• Payload for one hit
• 43758330 bits
• Group of 2
• 64/481.3
• Group of 3
• 96/482
• Group of 4
• 128/482.6
• Group of 2.5
• Data volume saving 1.5

BCO1
1
1
1
0
0
0
Tn(10)
Row1
Column1
Module
0
Chip
ADC0
ADC1
0
1
BCO2
1
1
1
0
0
0
Tn(10)
Row2
Column2
Module
ADC3
Chip
1
ADC0
ADC1
ADC2
BCO2
1
1
1
0
0
0
Tn(10)
Row24
Column2
Module
Chip
ADC4
0
0
1
9
Hit Group Composer (3-Hit Version)
Row2
Row1
Row0
Row (7 bits)
Row (7 bits)
Col2
Col1
Col0
Col (5 bits)
Col (5 bits)
BCO2
BCO1
BCO0
BCO (8 bits)
BCO (8 bits)
ADC2
ADC1
ADC0
ADC (3 bits)
ADC0,1,2 (9 bits)
(BCO1BCO0)
GT_1_hit
(Col1Col0)
(Row1(Row01))
(!Used0)
Eq_3_hits
(BCO2BCO1)
(Col2Col1)
(Row2(Row11))
Used0
Valid
Used1
About 120 Logic Cells
10
Not AffordableOne Hit Group Composer/Channel
Shift Register
Hold Register
Hit Group Composer
Ch. 0
Phase Detect
Frame Detect
Hit Group Composer
Phase Detect
Frame Detect
Ch. 1
FIFO
Hit Group Composer
Phase Detect
Frame Detect
Ch. 23
120 Logic Cells each. 72 Ch 8640 LC (32
xc3s1500)
11
Not AffordableEven Just Registers and MUX
Shift Register
Hold Register
Ch. 0
Phase Detect
Frame Detect
Phase Detect
Frame Detect
Ch. 1
FIFO
Hit Group Composer
120 Logic Cells each. 72 Ch 3x120360 LC OK But
need to keep track of the next hits.
Phase Detect
Frame Detect
Ch. 23
72 Logic Cells / channel 72 Ch 5184 LC (19
xc3s1500)
12
Delay Lines
Barrel Shifter
Delay Lines
Ch. 0
Phase Detect
Frame Detect
Bit 23
Phase Detect
Frame Detect
Ch. 1
FIFO
Hit Group Composer
Ch. 23
Phase Detect
Frame Detect
Bit 0
160 Logic Cells / 24 channel 72 Ch 500 LC (2
xc3s1500)
XAP149
13
Hit Group Composer
Shift Reg. 24
Shift Reg. 24
Row, Col, BCO
Row, Col, BCO
ADC0
ADC
ADC1
ADC2
Hit Grouping Logic
Hits
Valid
Used Word Pipe
Used Word Pipe
14
Ch. 0
Ch. 1
Ch. 23
Ch. 24
Ch. 47
Ch. 48
Ch. 71
15
Supporting Slides

• Details are shown in next a few slides.

16
Bit assignments (From DCC)
Pixel hit data Some header records BCO
header Half plane header Chip header
Col (5-bits)
0
Row (7-bits)
ADC
1
0000000
BCO high order
BCO
BCO
17
Same Column Groups
BCO header Half plane header Chip
header Pixel Data
1
0000000
BCO high order
BCO
BCO
18
Data Rates
Media /hwy Throughput capacities Data Rates /hwy Safety factors
PDCB to TSO 2.5 Gbps fibers 120 240 Gbps 29.5 Gbps 8.1
TSO to PP 500 Mbps x 4 pairs 160 320 Gbps 19.7 Gbps 16.2
PP to ST/L1B 500 Mbps x 4 pairs 128 256 Gbps (19.714.7) Gbps 7.4
ST/L1B to/from BM/Worker 500 Mbps x 2 pairs each way 128 128 Gbps lt (19.7/4) Gbps gt 26
ST/L1B to/from BM/Worker 500 Mbps x 2 pairs each way 128 128 Gbps 200 MB/s gt 64
BM to GL1 500 Mbps x 2 pairs each way 4 4 Gbps 47 MB/s gt 10
19
Input to L1 Trigger (Simplified from Doc 3342)
Idle
1
1
1
1
0
00
7
BCO Turn
BCO(70)
1
1
1
0
0
0
Tn(10)
Data word 0
Row
Column
Module
Data word 1 (repeat?)
ADC0
Chip
Hits
0
0
ADC1
ADC2
Status, Stn, hp. headers
Status etc.
1
1
1
1
0
0-6
Timing related info/headers
Timing Info etc.
1
1
1
0
0
1
0-3
Column
0
0
X
X
X
Invalid Column coding
1
1
1
X
0
20
Pixel Hit Grouping
Module
Row1
Column1
BCO1
ADC0
1
Chip
Module
Row11
Column1
ADC1
1
BCO1
Chip
Module
Row2
Column2
ADC0
1
BCO2
Chip
Module
Row21
Column2
ADC1
1
BCO2
Chip
Module
Row22
Column2
ADC2
1
BCO2
Chip
Module
Row23
Column2
ADC3
1
BCO2
Chip
Module
Row24
Column2
ADC4
1
BCO2
Chip

• Payload for one hit
• 43758330 bits
• Group of 2
• 64/481.3
• Group of 3
• 96/482
• Group of 4
• 128/961.3
• Group of 2.5
• Data volume saving 1.5

BCO1
1
1
1
0
0
0
Tn(10)
Row1
Column1
Module
ADC0
Chip
Hits2
0
0
ADC1
BCO2
1
1
1
0
0
0
Tn(10)
Row2
Column2
Module
ADC0
Chip
Hits3
0
0
ADC1
ADC2
BCO2
1
1
1
0
0
0
Tn(10)
Row23
Column2
Module
ADC3
Chip
Hits2
0
0
ADC4
21
BCO Header, Column Header
BCO1
1
1
1
0
0
0
Tn(10)

• The types of the words can be recognized from
  lower 5 bits. So they can be used either as data
  or header.
• If the BCO is sorted by PDCB, the BCO word can be
  used as header.
• The Column word can also be used as a header.
  However, it is not recommended since the
  instantaneous rate will be too high.
• The easiest is three-word fix-size data stream as
  shown in previous slide.

Row1
Column1
Module
ADC0
Chip
Hits2
0
0
ADC1
Row2
Column2
Module
ADC0
Chip
Hits3
0
0
ADC1
ADC2
BCO1
1
1
1
0
0
0
Tn(10)
Row1
Column1
Module
ADC0
Chip
Hits2
0
0
ADC1
Row2
Column2
Module
ADC0
Chip
Hits3
0
0
ADC1
ADC2
ADC3
Chip
Hits2
0
0
ADC4
22
The TSO and PP Stage (Half Highway)
From PDCB, 5x12 fibers, 2.5 Gb/s/fiber
To Segment Trackers, 8x8 cables, 1.5 Gb/s/cable
23
Supported Configuration5x8, Half Highway
TSO Modules
PP Modules
TSO Modules
PP Modules
CPU
P1
P2
24
The TSO Module

• Serial data from optical receiver are sent to
  FPGA devices at 2.5 Gb/s per channel.
• Time stamp ordering is done in FPGA and RAM.
• Time stamp ordered data are sent to the backplane
  connector at 300 500 Mb/s per pair.
• The data are sent to the PP modules via backplane.

Buff
FPGA VME
Buff
RAM
RAM
Buff
FPGA
FPGA
RAM
RAM
Optical Rec ZL60102
RAM
RAM
FPGA
FPGA
RAM
RAM
25
TSO Module
Buff
PTSM FPGA
VME P1
Buff
Buff
Optical Receiver
P2
26
Delay Lines
Delay Lines
Barrel Shifter
Hit Group Composer
FIFO
4
5
6
0
1
2
3
4
5
7
0
1
2
3
4
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
6
7
0
1
2
4
5
6
7
0
1
3
4
5
6
7
0
2
3
4
5
6
7
1
2
3
4
5
6
7
1
2
3
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0