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Source III, Inc.

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Verilog/VHDL. Testbench. STIL. WGL ... 2002 Synopsys, Inc. ( 4 ) CONFIDENTIAL. VTRAN's EDA-IP ... Simplifies translations by providing data access rather than ... – PowerPoint PPT presentation

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Title: Source III, Inc.


1
Source III, Inc.
Vector data translation for Simulation Test
  • John Cosley

2
VTRAN overview
  • Bridging simulation test formats
  • Focused on ATPG-generated translations
  • Comprehensive processing options
  • Large number of canned readers
  • STIL, WGL, VCD, TDL_91,
  • Numerous formatters for testers EDA
  • STIL, WGL, Credence, Teradyne, Agilent, IMS,

3
VTRAN Flow
VTRAN
Vector Formats VCD WGL STIL
OVF Original Vector File
TVF Target Vector File
Tools ATPG Simulators
Processing
Verilog/VHDL Testbench STIL WGL
Command File
4
VTRANs EDA-IP
5
STIL application overview
  • Vtrans STIL Reader
  • Support for 1450-1999
  • Partial (evolving) support for .1 extensions
  • User programmable flatten scan or not, flatten
    loops or not, flatten timing or not, pass
    Annotations or not, . . .
  • Procedures Macros expanded
  • Simplifies translations by providing data access
    rather than just structural access

6
STIL application overview
  • Vtrans STIL Writer
  • 1450-1999 syntax
  • Full support for scan Shift and Loops
  • User specified Signal groupings for file size and
    performance optimization
  • Numerous data processing options available to
    user e.g. signal masking, customized state
    translations, signal name ALIASing,

7
Current Status
  • STIL reader (1450-1999) in use today in
    conjunction with TetraMAX tested with files
    from Mentor Fastscan and IBM Testbench
  • STIL reader .1 support under development
  • STIL writer in use today at several customer
    sites
  • Limitations
  • Some reader syntax not implemented as yet
    InheritWaveform, SubWaveforms, Multi-bit data.

8
STIL Technical Issues
  • High degree of syntax flexibility (complexity)
    opens the door to unmappable constructs. E.g
    Waveforms, scan Shift blocks,
  • Context-sensitive syntax requires more software
    intelligence (processing/time).

9
Future STIL plans
  • Implement remaining .1 features at least those
    being used by ATPG vendors
  • Continue enhancements on Waveform mapping
  • Implement InheritWaveform and Multi-bit data
  • Continue verification with STIL files from more
    vendors
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