Basics of Logic Design

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Basics of Logic Design

• Panickos Neophytou
• CS0447
• 11/16 11/21

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Overview

• Boolean Algebra Review
• Logic Gates
• Multiplexors
• Verilog
• ALU design

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Boolean Algebra Review

• Operators
• OR written as , e.g. AB
• AND written as , e.g. AB
• NOT written as A
• Laws of Boolean Algebra
• Identity A0A and A1A
• Zero and One laws A11 and A00
• Inverse laws AA1 and AA0
• Commutative laws ABBA and ABBA
• Associative laws A(BC)(AB)C and
  A(BC)(AB) C.
• Distributive laws A(BC)(AB)(AC) and
  A(BC)(AB) (AC)

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Logic Gates

• Gate device that implements basic logic
  functions, such as AND or OR.

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Multiplexors

• E.g. Two-input multiplexor

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A 32bit wide 2-to-1 multiplexor
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Introduction to Verilog

• Data types
• wire In Verilog, specifies a combinational signal
• reg In Verilog, a register
• reg 310 X
• wire 310 X
• Refer to contigious set of bits of a register or
  wire by starting bit ending bit
• reg 310 registerfile031 An array of
  registers
• Possible values 0, 1 (true, false), z (unknown).

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Verilog

• 4b0100 4-bit constant with value 4, 4d4 same
• -8h4 8-bit constant with value -4 (in twos
  complement)
• 162b01 32-bit value 0101010101
• A3116,B150

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Verilog Operators

• Arithmentic ,-,,/
• Logical ,,
• Comparison ,!,gt,lt,gt,lt
• Shift ltlt,gtgt
• Unary logical ops ,, (e.g. A results in one
  bit by ANDing all of As bit together)

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Structure of Verilog Program

• Structured as a set of modules
• Module specifies inputs and outputs
• Body of a module consists
• Initial constructs
• Assignments
• always constructs
• Instances of other modules

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always construct

• Defines an optional list of constructs for which
  the block is sensitive
• Reevaluated if any of the specified signals
  changes value. If no list is specified the it is
  constantly reevevaluted.

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Assignments

• Blocking assignment
• Completed before the next assignment is carried
• Non-blocking assignment lt
• All right-hand sides of the assignments in an
  always block are done simultaneously.

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Example
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Construction a basic ALU

• A 1-bit ALU

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ALU

• Full adder

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Full Adder
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CarryOut calculator
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Sum

• The Sum bit is set when exactly one input is 1 or
  when all three inputs are 1.

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32-bit ALU adder
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ALU in verilog
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ALU control unit