FPGAs at U of I

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FPGAs at U of I

• Mike Haneym-haney_at_uiuc.edu

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Context

• recently obtained FPGAExpress
• have not looked carefully at it yet
• have VBPLD
• but this work predates that
• Therefore
• VeriBest may already do all this -)

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Needs

• application specific symbols
• application specific pin names
• specific PDB entries
• because of the pin names
• dynamic wrt pin numbers
• simulation support

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Altera and Xilinx

• mostly Altera...
• both nonvolatile and SRAM
• sometimes unique, sometimes shared
• most designs specific to a project
• but some get reused...

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Early attempts

• VBDC symbol edit
• source material from swft_pld_fpga.slb
• hand edit PDB text files
• hand written Verilog wrappers
• Altera produces Verilog
• xnf2vlog for Xilinx

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Why we stopped doing this

• Process is frequently repeated as the design
  evolves
• tedious
• error prone
• disgruntling
• So we starting writing some of our own tools

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Pname.exe (C)

• takes lttemplategt.inp and ltnamegt.fit
• ascii_out from swft_pld_fpga.slb
• ltnamegt.fit from Altera compiler
• and produces ltnamegt.inp
• graphics from lttemplategt
• pin names from .fit
• ascii_in gt symbol

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Pname (cont)

• strengths
• allow complex symbols
• VBDC-based symbol editing
• weaknesses
• labor intensive
• VBDC-based symbol editing

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Smaker.exe (C)

• successor to Pname
• takes ltnamegt.fit Package.dat (Altera)
• creates
• ltnamegt.inp
• ltnamegt._pdb.txt
• ascii_in gt symbol
• pdb_comp.bat gt cad.pdb

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Smaker (cont)
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SQFPGA.exe (C)

• takes text control file
• to be constructed from .xnf file (Xilinx)
• creates
• ltnamegt.inp
• ltnamegt_pdb.txt
• ascii_in gt symbol
• pdb_comp.bat gt cad.pdb

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SQFPGA

• PART_NAME XC5210
• PART_NUMBER XC5210PQ240-5
• SYMBOL_NAME GENERICXC5210-240
• VERILOG_MODEL IDUNNO
• INTERNAL_NAME ___IDUNNO___
• TOPCELL IDUNNO
• PARSE_ALG EXACTCORNER
• PIN_DEFINITIONS 240
• 1 GND S
• 2 GCK1-A16-IO B
• 3 A17-IO B

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pdb_comp.bat

• finds all pdb-related text files,and compiles
  them into cad.pdb
• cat _pdb.txt gt pdb_tmp.txt
• pdb_comp pdb_tmp.txt cad.pdb 1 N Y

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Vlog

• converts vectored signal Verilog
• module tracksum (wirea)
• input 130 wirea
• into discrete signal wrapper
• module tracksum_int (wirea13,wirea12,)
• input wirea13
• input wirea12
• suitable for discrete pin symbol

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fixvsh.tcl

• TCL script to fix escaped-index bug in
  generated Verilog
• mostly AWK
• converts (\GAIN4 ) to
  (\GAIN 4 )

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fixvsh.awk

• /\\ \\/ store0 split(0,temp,"")
  0temp1" "temp2 if(length
  (store) 1 ! length (0))
  0storeprint 0

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In progress

• gate-per-pin PDB entries
• prolog and epilog fixed
• drop-in SYMB definitionfrom Smaker, SQFPGA, etc.

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Gate-per-pin fixed prolog

• NAME EPM7032
• REF U
• GATE pin1 p1
• GATE pin2 p2
• etc.
• GATE pin44 p44
• GATE vccgate vp5
• PPROP supplyVCC vp5
• GATE gndgate g0

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Gate-per-pin user inserted

• !edit only the SYMB section below!
• SYMB EPM7032LC44 default
• pin1 IN/GCLR
• pin2 IN/OE2
• pin4 IO_MC16
• etc.
• pin42 IN/GCLK
• pin44 IN/OE1
• !edit only the SYMB section above!

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Gate-per-pin fixed epilog

• VEND EPM7032LC44-__ default
• INTERNAL ?PCC7032__44 default
• COMP pin1 1
• pin2 2
• vccgate 3
• etc.
• gndgate 43
• pin44 44
• TOPCELL XPLC44

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Next?

• Perl instead of TCL
• Leaner-meaner in-house scripts
• combined ascii_in and pdb compile
• similar support for small PLDs