Simulation and Metamorphosis

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Simulation and Metamorphosis

• Peter M. Maurer
• Baylor University

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Simulation Types I

• Event Driven / Oblivious
• Oblivious Simulation time is not dependent on
  input values
• Event Driven Simulation time is a function of
  the number of changes in gate input values

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Simulation Types II

• Compiled / Interpreted
• Compiled Simulation converts a circuit
  description into a program, which is then
  compiled to create the simulator for the circuit
• Interpreted simulation performs simulation based
  on a set of internal tables, which can be changed
  dynamically

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The Usual Combinations

• Levelized Compiled Code
• Oblivious
• Compiled
• Zero Delay
• Event Driven Simulation
• Event Driven
• Interpreted
• Unit Delay

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The Inversion Algorithm

• The First Metamorphic Algorithm
• Event Driven
• Eliminates intermediate net values
• Eliminates all NOT gates
• Eliminates XOR/XNOR Gates
• AND, OR, NAND, NOR are all the same
• At an activity rate of 60, is almost as fast as
  levelized compiled code

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Functions As Type Codes

• Gate-Simulation Example
• Old Style Structures
• Each Structure contains a type code
• Decode the type code to select a simulation
  routine
• Objects
• A different class is used for each gate-type
• Each class has its own simulation routine
• Functions accessed through a pointer table

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Polymorphism

• Create a base type
• Define a virtual function in the base type
• Define several derived types
• Override the virtual function in the derived
  types
• Calling the virtual function through the
  base-type pointer calls the function in the
  derived type

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Metamorphosis

• Function tables are used to support polymorphism
• Function tables are read only
• Metamorphosis requires read-write function
  tables, or generic function pointers
• Threaded-Code pointers can also be used

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Metamorphic State Machines

• Function Pointers are used for state codes
• Instead of the following code
• If StateCode A Then Call B
• We call B directly through a function pointer
• Used in the Inversion Algorithm to represent net
  states
• Used for everything in EVCF

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The EVCF Technique

• Internal States
• Net State 1/0 or Dominant/Non-Dominant Depending
  on Gate Type
• Gate State Number of Dominant Inputs
• Queue Status Output Events Queued/Not
• Monitored Net 1/0
• Queue Empty/Not-Empty
• Separate Gate/Net Structures

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Net/Event Structure
struct Net struct Net Next struct Net
Prev Address ProcessRoutine struct Gate
Output struct Gate Driver
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Event Processing Routines
EVUP Shp-gtProcessRoutine EVDN Shp2
Shp-gtOutput goto Shp2-gtUp EVDN Shp-gtProcess
Routine EVUP Shp2 Shp-gtOutput goto
Shp2-gtDown
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The Gate Structure
struct Gate struct Net Begin struct Net
End Address Up Address Down Address
Schedule struct Net QueueHead
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Gate Simulation Routines
 
DN0 shp shp-gtNext goto shp-gtProcessRoutine
UP0 shp2-gtUp UP1 shp2-gtDown DN1 goto
shp2-gtSchedule
UP1 shp2-gtUp UP2 shp2-gtDown DN2 shp
shp-gtNext goto shp-gt ProcessRoutine
DN1 shp2-gtUp UP0 shp2-gtDown DN0 goto
shp2-gtSchedule
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More Gate Simulation
UP2 shp2-gtUp UP3 shp2-gtDown DN3 shp
shp-gtNext goto shp-gt ProcessRoutine
DN2 shp2-gtUp UP1 shp2-gtDown DN1 shp
shp-gtNext goto shp-gt ProcessRoutine
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Queueing

• Single-List Processing is used
• When an event is queued, there may already be an
  event for the net in the queue
• Complementary events should cancel one another

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Queueing Routine
QUEUE shp2-gtSchedule DEQUEUE
shp2-gtEnd-gtNext shp2-gtHead-gtNext
shp2-gtHead-gtNext-gtPrev shp2-gtEnd
shp2-gtHead-gtNext shp2-gtBegin
shp2-gtBegin-gtPrev shp2-gtHead shp
shp-gtNext goto shp-gtRtn
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Dequeueing Routine
DEQUEUE shp2-gtSchedule QUEUE
shp2-gtBegin-gtPrev-gtNext shp2-gtEnd-gtNext
shp2-gtEnd-gtNext-gtPrev shp2-gtBegin-gtPrev shp
shp-gtNext goto shp-gtRtn
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Event Structures
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The End of a Chain

• The final element in a prelinked chain of event
  structures uses a different set of event handlers

EVUP1 shp-gtRtn EVDN1
shp-gtDriver-gtSchedule QUEUE
shp2 shp-gtGate goto shp2-gtUp
EVDN1 shp-gtRtn EVUP1
shp-gtDriver-gtSchedule QUEUE
shp2 shp-gtGate goto shp2-gtDown
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Queue Content

• Multiple Queues are used for zero-delay
  processing
• When one queue empties, it is necessary to
  advance to the next queue
• An array of queue head pointers are used
• Trailer elements mark the end of the queue and
  perform end-of-queue operations

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The Trailer Routines
TRAILER // All but last queue in array
shp-gtHead-gtNext shp shp-gtPrev shp-gtHead
shp (struct Net )(shp-gtGate) goto
shp-gtRtn   TRAILER1 // Last Queue in Array
shp-gtHead-gtNext shp shp-gtPrev shp-gtHead
return
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Monitored Nets

• Most nets have no value maintained for them
• Monitored nets require a current value
• A special fanout-branch event is added to each
  monitored net
• These monitor events calculate the value of the
  net
• The monitor event is not processed unless the net
  changes value

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Monitor Routines
MONITOR0 shp-gtProcessRoutine MONITOR1
(long)(shp-gtGate) '0' shp shp-gtNext
goto shp-gtRtn MONITOR1 shp-gtProcessRoutine
MONITOR0 (long)(shp-gtGate) '1' shp
shp-gtNext goto shp-gtRtn
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Performance Details

• Time Measured in CPU Seconds using UNIX /bin/time
  command
• SUN UltraSparc-II 300MHZ
• 128MB RAM
• Times are the difference between simulating
  50,000 random vectors and 50,000 vectors of all
  zeros.
• Each test was repeated several times and the
  results were averaged.

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Performance Results (CPU Sec)
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EVCF Summary

• The EVCF technique is many times faster than
  conventional event-driven simulation
• It is comparable in speed to the Inversion
  Algorithm, but considerably more versatile
• It is cache-friendly, the simulation kernel is
  about 1200 bytes long

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The Future

• BDD Simulation
• Boolean Equations
• Other Objects
• Metamorphic state machines
• One-Hot state machines
• New Ideas