Serial Communication Interface

1
Serial Communication Interface

• Brad Butcher
• Austin Chen
• Jeffrey Gould
• John Huey

2
Evaluation Form
3
Agenda

• Basic Definitions
• Detailed Information
• Concrete Examples

4
Learning Objectives

• Describe the Difference Between Serial and
  Parallel Communication
• Explain Asynchronous Communication
• Determine Time Needed to Transmit a Block of Data
• Describe a Common Error Detection Mechanism
• How to Implement SCI on HC11

5
Data Transmission Tree
Data Transmission

• Parallel

Serial
Synchronous
Asynchronous
6
Definition Parallel

• Data is sent and received more than one bit at a
  time
• Transmission on multiple wires

7
Definition Serial

• Data is sent and received one bit at a time
• Transmission on single wire

8
Why Serial?

• Fewer wires translates to
• Lower cost
• Simpler set-up

9
Definition Synchronous

• Sender and receiver have their clocks
  synchronized
• Transmissions occur at specified intervals
• Advantage
• Faster

10
Definition Asynchronous

• Devices are not synchronized
• Transmissions happen at unpredicted intervals
• Advantages
• Simpler
• More robust

11
Please Note

• Both synchronous and asynchronous must have
  agreed upon bit transfer rate

12
Why Asynchronous?

• Disadvantage
• Slower due to overhead
• Advantages
• Simpler
• Cheaper
• Information can be sent when ready

13
FYI Term UART

• Universal
• Asynchronous
• Receiver-
• Transmitter

• a computer component that handles asynchronous
  serial communication.
• www.webopedia.com

14
(No Transcript)
15
(No Transcript)
16
Definitions

• Start Bit
• Signals the beginning of the data word
• A low bit after a series of high bits
• Data Bits
• The meat of the transmission
• Usually 7 or 8 bits

17
Definitions Continued

• Parity Bit
• An error check bit placed after the data bits
• Can be high or low depending on whether odd
  parity or even parity is specified
• Stop Bit/s
• One or two high bits that signal the end or the
  data word
• Data Word
• Start Bit, Data Bits, Parity Bit, Stop Bit/s

18

• BAUD RATE
• BIT RATE

19
Baud Rate

• Baud Rate bits transferred/second
• baud rate INCLUDES start, stop, and parity
• bit rate refers to JUST data bits transferred
  per second (may include parity)
• baud rate gt bit rate

20
Baud Rate Example

• Calculate baud rate
• 1/bit time 1/9.09ms 110 baud
• Time to transmit word
• (11 bits) x (9.09ms) 0.1 s
• Word rate
• 1/0.1s 10 char/s
• Bit rate
• (10 char/s) x (8 bits/char) 80 bits/s

21
Error Minimization

• samples bit 3 times around center
• reduces drift error

1
noise
0
clock cycles
Samples at center 8 RT cycles
single bit width, 16 RT cycles
22
The Transmitter
23
The Transmitter

• Double Buffered
• Transmit Shift Register
• SCDR
• Break/Idle
• Break Signal - String of all zeros
• Idle Signal - String of all ones
• Resynchronizes or wakes up Receiver

24
The Transmitter

• Normal Transmission
• Interrupts
• Transmission Data Register Empty
• Transmission Complete
• Only one Interrupt Vector for the SCI
• ISR must read SCSR to determine which flag caused
  the interrupt

25
The Receiver
26
The Receiver

• Double Buffered
• Synchronizes internal clock (RT clock) with
  incoming data
• Internal clock runs 16 times faster than the baud
  rate
• 8 bit data tolerates 4.5 BAUD error
• 9 bit data tolerates 4 BAUD error
• Interrupt
• Receive Data Register Full

27
The Receiver

• Ready to receive
• Checks for Start bit
• Three highs followed by a low (RT clock resets)
• Checks RT3, RT5, RT7
• If any 2 are high, Receiver resumes search for
  Start Bit
• Checks RT8, RT9, RT10
• If ones are detected, NF set, but Start Bit still
  verified
• Checks each data bit
• Checks each RT8, RT9, RT10
• Goes with majority, but will set NF

28
Start Bit Check Ex.1
29
Start Bit Check Ex. 2
30
Start Bit Check Ex. 3
31
Receiver Wake Up

• Used for systems of multiple receivers
• Transmitter queues receivers to wake up from a
  sleep state
• Each Receiver checks beginning of message to see
  if message is for it
• RWU bit cleared by hardware when receiver is
  awoken

32
Receiver Wake Up (Idle Line)

• Idle condition sets RWU bit to zero
• Receiver is awoken
• Receiver checks beginning of message to determine
  if it is important to the receiver
• Receiver either accepts data or goes back to
  sleep
• Idle check more efficient in data transfer, but
  receivers remain awake between messages

33
Receiver Wake Up (Address-Mark)

• If MSB of data is 1, receivers awoken
• Receivers check beginning of message
• Either accept data or go back to sleep
• Address-Mark allows receivers to go to sleep
  between messages, but requires each character to
  set aside MSB as 1

34
Port D and the DDRD

• Receiver uses pin 0 of Port D and DDRD
• Overwrites DDRD0 pin
• Stores value of PD0 internally
• Restores condition of DDRD0 and info at PD0
• Transmitter uses pin 1 of Port D and DDRD
• Similar actions take place

35
BAUD-Rate Control Register

• HC11 assumes BAUD rate is 16 times slower than
  E-clock
• Transmitter and Receiver should be set at same
  BAUD rates

36
SCI Data Register

• Actually two registers
• RDR used by receiver - Read only!
• TDR used by transmitter -Write only!

37
Baud Rates of the HC11
     
Step 1  
38
Baud Rates of the HC11
     
Step 2  
39
SCI Status Register

• Interrupt possibilities
• TDRE - Transmit Data Register Empty
• 1 SCDR empty and ready for new character
• TC - Transmit Complete
• 1 Shift register is finished sending data
• RDRF - Receive Data Register Full
• 1 Receive Shift Register has pushed a character
  to the SCDR for reading

40
SCI Status Register

• IDLE - Idle-Line Detect
• 1 Receiver is in the Idle mode
• OR - Overrun Error
• 1 Receive Shift Register has finished receiving
  new character before old character has been read
  from the SCDR
• NF - Noise Flag
• 1 HC11s detected noise in a character
• FE - Framing Error
• 1 Noise detected in Start or Stop bit

41
SCI Control Register 1

• M - SCI Character Length
• 0 8 bit character
• 1 9 bit character
• R8 and T8 bits are the 9th bit in data characters
• 9th bit is either an extra stop bit, parity bit,
  or address marker

42
SCI Control Register 1

• WAKE bit
• 0 Idle Line -- Receiver waits for an idle line
  to wake up
• 1 Address mark -- Receiver waits for MSB of 1
  in the character to wake up

43
SCI Control Register 2

• Polling vs. Interrupts
• If the bits are set to 1, an interrupt happens
• If the bits are left 0, polling must be used
• TIE bit - TDRE flag
• TCIE bit - TC flag
• RIE bit - RDRF/OR flag
• ILIE bit - IDLE flag

44
SCI Control Register 2

• Transmitter/Receiver Enable
• 1 Enabled
• Miscellaneous
• RWU bit
• 1 Receiver asleep, no interrupts, receiver
  awoken according to WAKE bit condition of SCCR1
• SBK
• 1 Transmitter allowed to send Break signal

45
How to actually send/get data!Transmitter
Receiver

• Set Baud rate of transmitter
• Set M bit of SCCR1 for 8 or 9 bit data
• Set TE bit of SCCR2 high to enable transmitter

• Set Baud rate of receiver
• Set M bit of SCCR1 for 8 or 9 bit data
• Set RE bit of SCCR2 high to enable receiver

46
How to actually send/get data!Transmitter
Receiver

• Activate WAKE condition
• Load data character into SCDR
• When TDRE bit of SCSR register goes high, the
  SCDR register is clear and another character can
  be loaded

• Set WAKE bit on SCCR1

47
How to actually send/get data! Transmitter
Receiver

• When TC bit of SCSR register goes high, transmit
  buffer clear
• Transmitter resumes Idle

• RDRF bit of SCSR set when data has entered SCDR

48
How to actually send/get data! Transmitter
Receiver

• Check flags for possible error protocols
• Read SCDR and store data
• Receiver returns to wake/sleep mode previously set