8086 Interrupt Mechanism

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8086 Interrupt Mechanism
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NMI (Non-Maskable Interrupts) - Only one (Power
Failure - int 2) - Interrupt Handle Code is
addressed at 00000008 Special Interrupts (not
maskable) - Divide by Zero (int 0 , addressed at
00000000) INTR (Maskable Interrupts)
Interrupt Vector Table - first 256 X 4 bytes of
memory - interrupt vectors are number from 0 to
255 - multiply interrupt number by 4 to get
IPCS of interrupt service routine
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IF - Interrupt Flag - can bet set or cleared.
- STI set interrupt flag - CLI clear interrupt
flag Setting the IF to 1 will acknowledge
regular (maskable) interrupts
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-A device sets the interrupt line high - pin 18
INTR Mr. CPU, I need some help -The CPU
responds (when ready) by setting INTA high What
may I do for you -The device responds by
putting a number (0-255) on the data bus (address
into the interrupt vector table
BUT.what if there is more than one device ? We
need an interrupt controller chip (an 8259A to be
precise). All devices (up to 8) connect to the
chip and the chip connects to the INTR
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8259A Structure IMR (Interrupt Mask Register)
This register allows the programmer to disable
or "mask" individual interrupts so that the PIC
doesn't interrupt the processor when the
corresponding interrupt is signaled. For an
interrupt to be disabled, its corresponding bit
in the IMR must be 1. To be enabled, its bit
must be 0. Interrupts can be enabled or
disabled by the programmer by reading the IMR,
setting or clearing the appropriate bits, then
writing the new value back to the IMR. The
IRR (Interrupt Request Register ??) This
register indicates when an interrupt has been
signaled by a device. As soon as a device
signals an interrupt, the corresponding bit in
the IRR is set to a 1. This register can only
be modified by the PIC and its contents are
usually not important to the programmer.
However, it can be used to tell which
interrupts are waiting for service.
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ISR (In Service Register) This register indicates
which interrupts are currently being serviced
(i.e., which ISRs have begun execution and have
not yet finished). A 1 bit indicates that the
corresponding ISR is currently in-service.
Several interrupts can be in-service at the same
time because of interrupt nesting. The PIC uses
this register to determine the highest priority
of the interrupts currently being serviced. With
this information, the PIC will only interrupt the
processor if the highest priority set bit in the
IRR has a higher priority than the highest
priority set bit in the ISR. In other words, the
PIC will never interrupt an in-service interrupt
in order to service another interrupt of the
same or lower priority. Before an ISR finishes
executing, it must send to the PIC the end of
interrupt command (EOI) so that the PIC knows
that it can safely clear the highest priority
bit in the ISR and signal any other pending
interrupts.
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Programming the 8259A Each 8259A has two io
ports assigned to each of them. For simplicity
we'll call them port a and port b. The are
assigned as follows port a port b Master
8259A 0x20 0x21 Slave 8259A 0xA0 0xA1
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The 8259A is configured throught a series of 4
control words. To configure it send the first
word (ICW1) to port a and the rest are sent to
port b.
/ ICW1 / outb( 0x11, 0x20 ) / Master port A
/ outb( 0x11, 0xA0 ) / Slave port A / /
ICW2 / outb( 0x20, 0x21 ) / Master offset of
0x20 in the IDT / outb( 0x28, 0xA1 ) / Master
offset of 0x28 in the IDT / / ICW3 / outb(
0x04, 0x21 ) / Slaves attached to IR line 2
/ outb( 0x02, 0xA1 ) / This slave in IR line 2
of master / / ICW4 / outb( 0x05, 0x21 ) /
Set as master / outb( 0x01, 0xA1 ) / Set as
slave /