Flip-Flops and Related Devices

1
Flip-Flops and Related Devices

• Chapter 8

2
S-R (SET-RESET) Latch
Active-HIGH input Active-LOW input S-R
Latch S-R Latch
3
S-R (SET-RESET) Latch
4
S-R Latch Logic Symbol
5
Switch Contact De-bounce. Figure 8--6
6
When the set is high and reset is low Q is high
and Q is low
7
Once set ie Q high, then with S and R both low
nothing change.
8
With reset high and set low the flipflop give a
Q high and a Q low.
9
Toggling the reset changes nothing
10
The state of both set and rest high is not
allowed since it would give a illogical condition.
11
S-R flip flop truth table for NOR flip-flop
S R Q Q 0 0 Q Q hold condition 1 0 1 0 set 0
1 0 1 reset 1 1 0 0 not allowed
12
S-R flip flop using NANDs
Set high reset low Q high Q low
13
Reset high set low give a Q low and Q high
14
Both low no change
15
Both set and reset high is not allowed but give
both Q and Q as high
16
S-R flip flop truth table for NAND flip-flop
S R Q Q 0 0 Q Q hold condition 1 0 1 0 set 0
1 0 1 reset 1 1 1 1 not allowed
17
S-R flip flops do not come ready made but a 7402
dual 2input NOR came be used to make the S-R flip
flops
18
Gated SR Latch

• A gate input is added to the S-R flip-flop to
  make the flip-flop synchronous.
• In order for the set and reset inputs to change
  the flip-flop, the gate input must be active
  (high).
• When the gate input is low, the flip-flop
  remains in the hold condition.

19
With the Gate high the set is set and Q is high
Q is low
20
When the Gate is low nothing can change
21
When the gate is high
The flip flop works
22
Truth Table for S-R gated Flip Flop
S R G Q Q 0 0 0 Q Q Hold 1 0 0 Q Q Hold 0 1
0 Q Q Hold 1 1 0 Q Q hold 0 0 1 Q Q hold 1 0
1 1 0 set 0 1 1 0 1 reset 1 1 1 0 0 not
allowed
23
Gated D Latch

• The D (data) flip-flop has a single input that
  is used to set and to reset the flip-flop.
• When the gate is high, the Q output will follow
  the D input.
• When the gate is low, the flip-flop is latched.

24
Edge-triggered Flip-flop Logic Symbols
25
Edge Triggered SR Flip-flop
26
The J-K flip-flop has a toggle mode of operation
when both J and K inputs are high.Toggle means
that the Q output will change states on each
active clock edge. J, K and Cp are all
synchronous inputs. The master-slave flip-flop
is constructed with two latches. The master latch
is loaded with the condition of the J-K inputs
while the clock is high. When the clock goes low,
the slave takes on the state of the master and
the master is latched. The master-slave is a
level-triggered device. The master-slave can
interpret unwanted signals on the J-K inputs.
27
J and K are low so nothing will change are the
clock
28
No change
29
K is high and J is low at the next clock Q should
go low
30
The clock occurred Q went low
31
J is high K is low at the next clock Q should go
high
32
Q went High
33
I would love to show this circuit Toggle but it
will not since the Mater S-R flip flop is seeing
a not allowed 1 1 input and putting out a 0 at Q
and Q both.
34
But This Will Toggle
1
2
3
35
Truth Table for J-K Flip Flop
J K Q 0 0 Q Hold 1 0 1 Set 0 1 0 Reset 1 1 Q Togg
le
36

• The edge-triggered J-K will only accept the J and
  K inputs during the active edge of the clock.
• The small triangle on the clock input indicates
  that the device is edge-triggered.
• A bubble on the clock input indicates that the
  device responds to the negative edge. no bubble
  would indicate a positive edge-triggered device.

37
J and K are both high, this means a toggle at the
negative edge of the clock
38
Toggle
Toggle
Remain the same
Reset
Reset
39
Flip-Flop Operating Characteristics

• Propagation Delay Times
• Set-up Time
• Hold Time
• Maximum Clock Frequency
• Pulse Width
• Power Dissipation

40
Propagation Delay

• Clk to Output Q

• Preset and CLR to Output Q

41
Setup Time and Hold Time

• Setup Time

• Hold Time

42
Flip-Flop Applications

• Parallel Data Storage
• Frequency Division
• Counting

43
Parallel Data Storage. Figure 8--35
44
Divide-by-2 Device. Figure 8--36
45
Divide-by-4 Device. Figure 8--37
46
Divide-by-8. Figure 8--38
47
A race condition occurs when the data inputs (J-K
or D) to a flip-flop are changing at the same
time as the active clock transition.
The top J-K Flip Flop should not work due to a
race condition
The bottom J-K flip flop should work
48
Top Flip Flop Top Clock Bottom Flip Flop Bottom
delayed clock
49
Set-up time is the time that the data inputs to a
flip-flop must be set before the active clock
transition.
20ns of set up time is required for the J-K flip
flop to accept the high at K
50
Hold time is the amount of time that the data
inputs must maintain their level after active
clock transition.
The clock in blue is after the active K in red
the flip flop will not work
51
The clock is in red. The K input is in blue Note
the 26 ns hold time
52
The time required for the Q output to change as a
result of some input is called the propagation
delay. tPLH is the propagation delay when the Q
output goes from low to high.
I see 7.7ns for tPLH
53
tPHL is the propagation delay when the Q output
goes from high to low.
I see 7.6ns for tPHL since the blue is the output
and the red is the clock
54
The propagation delay can be caused by an
asynchronous input (RD or SD) or a synchronous
input (Cp).
The output Q goes low with the clock not shown.
The out put goes high due to a preset note the
10ns tPLH caused by the preset
55

• There are several other parameters that will also
  be listed in a manufacturers data sheet.
• Maximum frequency (Fmax) - The maximum frequency
  allowed at the clock input.
• Clock pulse width (LOW) tW(L) - The minimum
  width that is allowed at the clock input during
  the LOW level.
• Clock pulse width (HIGH) tW(H) - The minimum
  width that is allowed at the clock input during
  the high level.
• Set or Reset pulse width (LOW) tw(L) - The
  minimum width of the LOW pulse at the set or
  reset inputs.

56
Basic Operation of a 555 Timer

• Threshold
• Control Voltage
• Trigger
• Discharge
• Reset
• Output

57
Functional Diagram of 555 Timer
58
The 555 Timer Connected as a One-shot. Figure
8--49
59
One-shot Operationof the 555 timer. Figure 8--50
60
555 Timer as a One Shot
tw 1.1R1C1 1.1(2000?)(1?F) 2.2ms
61
555 Timer as a One Shot waveform
62
Astable operation of 555 Timer
tH .7 (R1R2)C1 2.1ms tL .7R2C1 0.7ms
63
Astable operation of 555 Timer
64
Astable operation of 555 Timer
65
Astable operation of 555 Timer
66
Less Than 50 Duty Cycle. Figure 8--54
67
Example 8-14. Figure 8--55
68
Astable operation of 555 Timer waveform
69
Registered Logic inProgrammable Logic Devices

• Registered refers to the use of a flip-flop
• The flip-flop is used to store the result of a
  logic function
• The flip-flop may be a D flip-flop of be
  programmable to operate as a J-K of S-R flip-flop

70
Generic CPLD/FPGA Registered Logic
71
Select Elements

• Are multiplexers or data selectors
• They are programmed to pass one input
• They will have 2 or more inputs FF control select
  can be programmed to pass the combinational
  output function or another control signal to the
  FF input
• Register bypass can be programmed to
• Route the output of the combinational generator
  to an output
• Route the output of the combinational generator
  to an interconnect
• Store it in the flip-flop

72
Select Elements
Registered
Combinational
73
Latches and Flip-flops Using VHDL

• The S-R latch can be either high or low inputs
• Q and QNOT are both inputs and outputs, VHDL has
  a bi-directional mode inout which is used in the
  port statement

port( S, R in std_logic Q, Qnot inout
std_logic)
74
S-R Latch in VHDL
library ieee use ieee.std_logic_1164.all entity
SRlatch is port( S, R in std_logic Q,
Qnot inout std_logic) end entity SRlatch
75
S-R Latch in VHDL Continued
architecture Latch_Operation of SRlatch is begin
process(S,R) is begin Q lt Qnot nor
S Qnot lt Q nor R end process end
architecture Latch_Operation
76
S-R Latch to S-R Flip-flop

• The S-R flip-flop may use a clock pulse
• The clock pulse needs to be an edge trigger event
• Using the VHDL statement wait until rising_edge
  (clock) will cause the program to be driven by
  the the clock
• Use the statement falling_edge for negative edge
  triggered

77
S-R Flip-flop in VHDL Example 8-16
library ieee use ieee.std_logic_1164.all entity
SRFlipFlop is port( S, R, Clock in
std_logic Q, Qnot inout std_logic) end entity
SRFlipFlop
78
S-R Flip-flop in VHDL Example 8-16
architecture FlipFlopBehavior of SRFlipFlop
is begin process (S, R, Clock) is
begin wait until rising_edge (Clock) if S1
and R0 then Q lt1 elseif S0 and R1
then Q lt0 else Q ltQ end if Qnot lt
not Q end process end architecture
FlipFlopBehavior
79
J-K Flip-flop in VHDL Example 8-17
J K Q 0 0 Q Hold 1 0 1 Set 0 1 0 Reset 1 1 Q Togg
le
library ieee use ieee.std_logic_1164.all entity
JKFlipFlop is port( J, K, Clock in
std_logic Q, Qnot inout std_logic) end entity
JKFlipFlop
80
J-K Flip-flop in VHDL Example 8-17
architecture FlipFlopBehavior of JKFlipFlop
is begin process (J, K, Clock) is
begin wait until rising_edge (Clock) if J1
and K0 then Q lt1 elseif J0 and K1
then Q lt0 elseif J1 and K1 then Q
ltQnot else QltQ end if Qnot lt not
Q end process end architecture
FlipFlopBehavior
81
D Flip-Flop

• Use the S-R flip-flop and and an inverter

82
D-Flip-Flop VHDL code
library ieee use ieee.std_logic_1164.all entity
D_flip_flop is port( D, Clock in std_logic
Q, Qnot inout std_logic) end entity D_flip_flop
83
D-Flip-Flop VHDL Code continued
architecture Flip_Flop_Behavior of D_flip_flop
is begin process(D, Clock) is begin
wait until rising_edge (clock) if D 1
then Q lt 1 else Q lt
0 end if Qnot lt not Q end
process end architecture Flip_Flop_Behavior
84
Re-usable Packages

• Make S-R latch a package and use it many times
• Using a VHDL package allows the use of the S-R
  latch in the construction of other logic devices

library ieee use ieee.std_logic_1164.all packag
e SRPackage is procedure ActiveLowSRlatch (
Snot, Rnot in std_logic Q, Qnot inout
std_logic) end entity SRPackage
85
Re-usable Packages
package body SRPackage is procedure
ActiveLowSRlatch (Snot, Rnot in std_logic Q,
Qnot inout std_logic) is begin if Snot 1
and Rnot0 then Q 0 Qnot1
elseif Snot0 and Rnot1 then
Q1 Qnot0 elseif Snot0 and
Rnot0 then QQnot Qnot not Q end
if end ActiveLowSRlatch end SRPackage
86
Re-usable Packages Example 8-18

• Active Low JK flip-flop with positive edge using
  SRPackage
• Library work

library ieee, work use ieee.std_logic_1164.all u
se work.SRPackage.all entity ActiveLowJK is
port ( Jnot, Knot, clock in std_logic X, Y
out std_logic) end entity ActiveLowJK
87
Re-usable Packages Example 8-18
architecture JKBehavior of ActiveLowJK
is begin process (Jnot, Knot) variable V1, V2
std_logic begin wait until rising_edge
(clock) FF1ActiveLowSRlatch (SnotgtJnot,
RnotgtKnot, QgtV1, QnotgtV2) XltV1
YltV2 end process end architecture
JKBehavior
88
J-K Flip-Flop Components

• In Example 8-17 a a modified S-R latch package
  was used to define the J-K flip-flop
• The J-K flip-flop will be made into a component
  for used in a frequency divider

component JKFlipFlop is port( J,K,Clock in
std_logic Q, Qnot inout std_logic) end
component JKFlipFlop
89
VHDL Keyword buffer

• Similar to in, out, and inout used in a port
  statement
• buffer is unidirectional

port(clock in std_logic Qa, Qb, Fout buffer
std_logic)
90
Component and Buffer in VHDL Example 8-19
library ieee use ieee.std_logic_1164.all entity
FreqDivider is port ( clock in std_logic
Qa, Qb, Fout buffer std_logic) end entity
FreqDivider
91
Component and Buffer in VHDL Example 8-19
architecture FreqDivBehavior of FreqDivider
is component JKFlipFlop is port (J, K, Clock in
std_logic Q inout std_logic) end component
JKFlipFlop signal I std_logic begin Ilt1 FFA
JKFlipFlop port map (JgtI, KgtI, Clockgtclock,
QgtQa) FFB JKFlipFlop port map (JgtI, KgtI,
ClockgtQa, QgtQb) FFC JKFlipFlop port map
(JgtI, KgtI, ClockgtQb, QgtFout) end
architecture FreqDivBehavior
92
VHDL Software

• Use working code to make more complex code
• Complex operations can often be better described
  using the behavioral approach
• The VHDL complier will decide how to implement
  the code and will know from the program
  statements whether it will be registered or
  combinational
• This allows the code to be usable on other
  programmable devices

93
End of Chapter 8
94
Counters

• Chapter 9

95
2-Bit Asynchronous Counter
96
2-Bit Asynchronous Counter
Clock Q0 Q0(LSB) Q1(MSB)
97
3-Bit Asynchronous Counter
98
3-Bit Asynchronous Counter
CLK Q0 Q1 Q2
99
Propagation Delays in 3-bit Asynchronous (Ripple)
Counter
100
Asynchronous Decade Counter

• The modulus of a counter is the number of unique
  states that the counter will sequence through.
• The maximum modulus is 2n where n is the number
  of flip-flops.

101
Asynchronous Decade Counter
CLK Q0 Q1 Q2 Q3
102
2-Bit Synchronous Counter
CLK Q0 Q1
103
3-Bit Synchronous Counter
CLK Q0 Q1 Q2
104
4-Bit Synchronous Counter
CLK Q0 Q1 Q2 Q3
105
4-Bit Synchronous Decade Counter
CLK Q0 Q1 Q2 Q3
106
Up/Down Synchronous Counters
CLK Q0 Q1 Q2 UP/Down
107
Design of Synchronous Counter
108
Cascade or Ripple Counter Counting Down
CLK Q0 Q1 Q2
109
Step 1 State Diagram
110
Step 2 Next State Table
111
Step 3 Flip-Flop Transition Table
112
Step 4 Karnaugh Maps
113
Step 5 and Step 6 Logic Expressions and Counter
Implementation
CLK Q0 Q1 Q2
114
Counter Decoding
115
Counter Applications Digital Clock
116
Logic Symbols
117
2-bit Asynchronous Binary Counter Using VHDL
The clock will be input C. FF0 the first
Flip-flop FF1 the second flip-flop
118
2-bit Asynchronous Binary Counter Using VHDL
entity TwoBitCounter is port(clock in
std_logic Qa, Qb buffer std_logic) end entity
TwoBitCounter architecture CounterBehavior of
TwoBitCounter is component JKFlipFlop is port(
J, K, Clock in std_logic Q, Qnot inout
std_logic) end component JKFlipFlop
119
2-bit Asynchronous Binary Counter Using VHDL
signal I std_logic begin I lt 1
FF0JKFlipFlop port map (JgtI, KgtI, Clock
gtclock, QnotgtQnot, QgtQa) FF1JKFlipFlop
port map (JgtI, KgtI, ClockgtQnot, QgtQb) end
architecture CounterBehavior
120
Asynchronous Truncated Counters
To truncate a counter a clear function must be
added to the J-K flip-flop component
JKFlipFlopClear is port( J, K, Clock, Clr in
std_logic Q, Qnot inout std_logic) end
component JKFlipFlopClear
121
Asynchronous Truncated Counters Example 9-11
Asynchronous MOD6 (0,1,..5) JK flip-flop with
clear
library ieee use ieee.std_logic_1164.all entity
ModSixCounter is port(clock in std_logic
Clr in std_logic Q0, Q1, Q2 buffer
std_logic) end entity ModSixCounter
122
Asynchronous Truncated Counters Example 9-11
architecture CounterBehavior of ModSixCounter
is signal Clear std_logic component
JKFlipFlopClear is port (J, K, Clr, Clock in
std_logic Q, Qnot inout std_logic) end
component JKFlipFlopClear signal I
std_logic begin I lt 1 Clear lt not (Q1
and Q2) FF0 JKFlipFlopClear port map (JgtI,
KgtI, ClrgtClear, Clock gtclock, QgtQ0) FF1
JKFlipFlopClear port map (JgtI, KgtI, ClrgtClear,
ClockgtQ0, QgtQ1) FF2 JKFlipFlopClear port
map (JgtI, KgtI, ClrgtClear, ClockgtQ1,
QgtQ2) end architecture CounterBehavior
123
Synchronous Counters in VHDL

• Synchronous refers to events that occur
  simultaneously
• For synchronous counters all flip-flops are
  clocked at the same time using the same clock
  pulse
• An example in VHDL would be to use the J-K
  flip-flop defined as a component then have it
  clocked using the same clock pulse

Figure 9-13
124
Synchronous Counters in VHDL
entity FourBitSyncCounter is port( I, clock
in std_logic Q0, Q1, Q2, Q3 buffer
std_logic) end entity FourBitSyncCounter
architecture CounterBehavior of
FourBitSyncCounter is signal S0, S1, S2
std_logic component JKFlipFlop is port(J, K,
Clock in std_logicQ, Qnot inout std_logic) end
component JKFlipFlop
125
Synchronous Counters in VHDL
begin FF0 JKFlipFlop port map (JgtI, KgtI,
Clockgtclock, QgtQ0) S0lt Q0 FF1
JKFlipFlop port map (JgtS0, KgtS0, Clockgtclock,
QgtQ1) S1 lt Q0 and Q1 FF2 JKFlipFlop
port map (JgtS1, KgtS1, Clockgtclock, QgtQ2)
S2 lt Q0 and Q1 and Q2 FF3 JKFlipFlop port
map (JgtS2, KgtS2, Clockgtclock, QgtQ3) end
architecture CounterBehavior
126
3-Bit Gray Code CounterExample 9-13
127
3-Bit Gray Code CounterExample 9-13
library ieee use ieee.std_logic_1164.all entity
StateCounter is port(clock in std_logic Q
buffer std_logic_vector(0 to 2) ) end entity
StateCounter
128
3-Bit Gray Code CounterExample 9-13
architecture CounterBehavior of StateCounter
is begin process (Clock) begin if Clock 1
and Clock event then case Q is when 000 gt
Q lt 010 when 010 gt Q lt 110 when
110 gt Q lt 100 when 100 gt Q lt
101 when 101 gt Q lt 001 when 001
gt Q lt 000 when others gt Q lt 000 end
case end if end process end architecture
CounterBehavior
129
End of Chapter 9
130
Shift Registers

• Chapter 10

131
Basic Shift Register Functions

• Data Storage
• Data Movement
• D flip-flops are use to store and move data

132
Basic Shift Register Functions
133
Serial in/Serial out Shift Registers
CLK Serial in Serial Out
134
Serial in/Serial out Shift Registers
135
5-Bit Serial Shift RegisterExample 10-1
136
8-bit Shift Register
137
Serial in/Parallel out shift registers
After 4 clock pulses, 0110
138
8-bit Serial in/Parallel Out
139
Timing Diagram for 8-bit Serial in/Parallel Out
CLR Data In QA QB QC QD QE QF QG QH CLK
140
4-Bit Parallel in/ Serial out Shift Register
141
4-Bit Parallel in/ Serial out Shift Register
Example 10-3
142
8-bit Parallel Load Shift Resister
143
Timing Diagram for 8-bit Parallel Load Shift
Resister
Loaded 10101010 Output 10101010
Shift/Load Output D0 D1 D2 D3 D4 D5 D6 D7 CLK
144
Parallel in/ Parallel out Shift Register
145
Bidirectional Shift Registers

• Data can be shifted left
• Data can be shifted right
• A parallel load maybe possible
• 74HC194 is an bidirectional universal shift
  register

146
Bidirectional Shift RegistersExample 10-4
147
74194 data table
_____ MODE SERIAL
PARALLEL OUTPUTS CLEAR S1 S0 CLK
LEFT RIGHT A B C D QA QB
QC QD ---------------------------------------
------------------------------------------------
--- 0 X X X X
X X X X X 0
0 0 0 1 X X 0
X X X X X X
QA0 QB0 QC0 QD0 1 1 1
POS X X a b c d
a b c d 1
0 1 POS X 1 X
X X X 1 QAn QBn QCn 1
0 1 POS X 0 X
X X X 0 QAn QBn QCn 1
1 0 POS 1 X
X X X X QBn QCn QDn 1 1
1 0 POS 0 X
X X X X QBn QCn QDn 0 1
0 0 X X X
X X X X QA0 QB0 QC0 QD0
148
74194
149
74194 parallel load
CLR S1 S0 QA QB QC QD SR SL A B C D CLK
150
74194 shift right
CLR S1 S0 QA QB QC QD SR SL A B C D CLK
151
74194 shift left
CLR S1 S0 QA QB QC QD SR SL A B C D CLK
152
Johnson Counter
CLK Q0 Q1 Q2 Q3
153
Ring Counter
CLK Q0 Q1 Q2 Q3
154
Shift Register Application
155
UART Universal Asynchronous Transmitter
156
Logic Symbols with dependency notation
157
VHDL Code for a Positive-edge Triggered D
Flip-flop
D flip-flop that will be used as a component.
library ieee use ieee.std_logic_1164.all entity
DFlipFlop is port( D, clock in std_logic Q,
Qnot inout std_logic) end entity DFlipFlop
158
VHDL Code for a Positive-edge Triggered D
Flip-flop continued
architecture FlipFlopBehavior of DFlipFlop
is begin process(D, Clock) is begin
wait until rising_edge (clock) if D 1
then Q lt1 else Q
lt0 end if end process Qnot lt
not Q end architecture FlipFlopBehavior
159
4-Bit Serial in/Serial out Shift Registers Using
VHDL Example 10-7
library ieee use ieee.std_logic_1164.all entity
SISOReg is port( I, clock in std_logic
Qout buffer std_logic) end entity SISOReg
160
4-Bit Serial in/Serial out Shift Registers Using
VHDL Example 10-7
architecture ShiftRegBehavior of SISOReg
is signal Q0, Q1, Q2 std_logic component
DFlipFlop is port (D, Clock in std_logic Q,
Qnot inout std_logic) end component
DFlipFlop begin FF0 DFlipFlop port map
(DgtI, Clock gtclock, QgtQ0) FF1 DFlipFlop
port map (DgtQ0, Clockgtclock, QgtQ1) FF2
DFlipFlop port map (DgtQ1, Clockgtclock,
QgtQ2) FF3 DFlipFlop port map (DgtQ2,
Clockgtclock, QgtQout) end architecture
ShiftRegBehavior
161
4-Bit Serial in/Parallel out Shift Registers
Using VHDL Example 10-8
library ieee use ieee.std_logic_1164.all entity
SIPOReg is port( I, clock in std_logic Q0,
Q1, Q2, Q3 buffer std_logic) end entity SIPOReg
Defined as an output.
162
4-Bit Serial in/Parallel out Shift Registers
Using VHDL Example 10-8
architecture ShiftRegBehavior of SIPOReg
is signal Q0, Q1, Q2 std_logic component
DFlipFlop is port (D, Clock in std_logic Q,
Qnot inout std_logic) end component
DFlipFlop begin FF0 DFlipFlop port map
(DgtI, Clock gtclock, QgtQ0) FF1 DFlipFlop
port map (DgtQ0, Clockgtclock, QgtQ1) FF2
DFlipFlop port map (DgtQ1, Clockgtclock,
QgtQ2) FF3 DFlipFlop port map (DgtQ2,
Clockgtclock, QgtQout) end architecture
ShiftRegBehavior
163
Parallel in/Serial out Shift Registers
function ShiftLoad (A, B, C, in std_logic)
return std_logic is begin return ((A and
B) or (not B and C)) end function ShiftLoad
164
Parallel in/Serial out Shift RegistersExample
10-9
library ieee use ieee.std_logic_1164.all entity
PISOReg is port( SL,D0,D1,D2,D3, clock in
std_logic Qout buffer std_logic) end entity
PISOReg
165
Parallel in/Serial out Shift RegistersExample
10-9
architecture ShiftRegBehavior of PISOReg
is function ShiftLoad (A, B, C in std_logic )
return std_logic is begin return (( A and B )
or ( not B and C )) end function
ShiftLoad signal S1, S2, S3, Q0, Q1, Q2
std_logic component DFlipFlop is port (D,
Clock in std_logic Q, Qnot inout
std_logic) end component DFlipFlop begin
SL1 S1 lt ShiftLoad (Q0, SL, D1) SL2 S2 lt
ShiftLoad (Q1, SL, D2) SL3 S3 lt ShiftLoad
(Q2, SL, D3) FF0 DFlipFlop port map (DgtD0,
Clock gtclock, QgtQ0) FF1 DFlipFlop port map
(DgtS1, Clockgtclock, QgtQ1) FF2 DFlipFlop
port map (DgtS2, Clockgtclock, QgtQ2) FF3
DFlipFlop port map (DgtS3, Clockgtclock,
QgtQout) end architecture ShiftRegBehavior
166
Bidirectional Shift Registers in VHDL
library ieee use ieee.std_logic_1164.all entity
BidirectionalCtr port(RL, I, clock in
std_logic Q0, Q1, Q2, Q3 buffer std_logic) end
entity BidirectionalCtr
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Bidirectional Shift Registers in VHDL
architecture ShiftRegBehavior of Bidirectional
is function RightLeft(A, B, Cin std_logic)
return std_logic is begin return ((A and
B) or (not B and C)) end function RightLeft
signal S0, S1, S2, S3 std_logic component
DFlipFlop is port( D, Clock in std_logic
Q, Qnot inout std_logic) end component
DFlipFlop
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Bidirectional Shift Registers in VHDL
begin SL0 S0 lt RightLeft(I, RL, Q1) SL1
S1 lt RightLeft(Q0, RL, Q2) SL2 S2 lt
RightLeft(Q1, RL, Q3) SL3 S3 lt
RightLeft(Q2, RL, I) FF0 DFlipFlop port map
(DgtS0, Clockgtclock, QgtQ0) FF1 DFlipFlop
port map (DgtS1, Clockgtclock, QgtQ1) FF2
DFlipFlop port map (DgtS2, Clockgtclock, QgtQ2)
FF3 DFlipFlop port map (DgtS3, Clockgtclock,
QgtQ3) end architecture ShiftRegBehavior
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End of Chapter 10