8086/8088 Architecture

1
8086/8088 Architecture

• Seven categories of signals.
• Max/min mode min mode is used for single procss.
  Max mode is used for multiprocss
• Test synchronize multiple processors
• Data Enable generally connected to biriectional
  buffer to isolate MPU from system bus.
• Data tran/rcvr controls data flow.
• IO or memory indicates whether the proc cycle is
  memory operation or IO operation.
• Bus High Enable enble the higher order byte of
  16 bit data

Power clock
BHE/S7 A19/S6 A16/S3 AD15 AD0 ALE M/IO RD
WR DEN DT/R
VCC CLK
MuX add status signals
GND
INTR NMI HOLD READY RESET
External rqst
Mux add and data buses
Response to External rqst
INTA HOLDA
Control status signals
Multipro envrnmnt
TEST MN/MX
2
Max/min mode control signals
Pin Min mode Max mode
24 INTA QS1 queue status signal
25 ALE QS0 queue stat signal
26 DEN S0 input sig to bus control
27 DT/R S1
28 M/IO S2
29 WR Lock to prvnt another proc from gaining control
30 HLDA RQ/GT1 enable another processor to gain control
31 HOLD RQ/GT0
3
Programming model
AX
BX
CX
DX
SP
BP
SI
DI
CS
DS
SS
ES
IP